Taiwan Semiconductor Manufacturing Comp. Ltd.

Wei-Ming You

Ting-Chun Wang

Cheng-Ta Wu

Lun-Kuang Tan

Huicheng Chang

Liang-Yin Chen

Su-Hao Liu

Kuo-Ju Chen

Chia-Cheng Chen

Huai-Tei Yang

Chun-Hung Wu

Chang-Miao Liu

Shiu-Ko JangJian

Yu-Ting Lin

Ching-Hwanq Su

Chih-Cherng Jeng

Yi-Hsien Lee

Ziwei Fang

Huang-Lin Chao

Che-Hao Chang

Jih-Churng Twu

I-Ming Chang

Sheng-Wen Chen

Tsung-Han Wu

Cheng-Wei Chen

Hong-Yi Wu

Chi-Ying Wu

Liang-Yu Yen

Yu-Ting Hsiao

Lan Fang Chang

Kuo-Cheng Lee

Kei-Wei Chen

Chih-Hung Chen

Yu-Sheng Wang

Chih-Cheng Lin

Hui-Chi Huang

Tsung-Chieh Tsai

Pin Chia Su

Han-Liang Tseng

Chih-Kang Chao

Yao-Wen Hsu

Chun-Hao Kung

Kao-Feng Liao

Yi-Hung Chen

Chin-Hsiung Ho

Shi-Ming Wang

Yen-Hsung Ho

Chia-Chun Cheng

Chi-Shen Lo

Jie-Huang Huang

Ming-Dar Guo

Cheng-Jung Sung

Pey-Yuan Lee

Fu-Su Lee

Yu-Chien Hsiao

Ming Te More

Yu-Shen Shih

Jiunn-Nan Lin

Ruey-Yong Deng

Ching Shan Lu

Sian-Ren Horng

Sheng-Hsiung Tseng

Yao-Pin Huang

Chang-Maio Liu

J W Wu

Tsung Han Wu

Fu-Sheng Guo

Yu-Peng Lin

Sheng-Chien Tung

Cheng Wei Chen

Jian-Hua Huang

Yu-Lin Du

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an isolation layer over the base portion and surrounding the fin portion. The semiconductor device structure includes a metal gate stack over the isolation layer and wrapping around an upper part of the fin portion. The metal gate stack includes a gate dielectric layer and a metal gate electrode layer over the gate dielectric layer, and the gate dielectric layer includes fluorine. A first part of the isolation layer is not covered by the metal gate stack, the first part includes fluorine, and a first concentration of fluorine in the first part increases toward a first top surface of the first part.

Semiconductor device structure having gate dielectric layer

The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

Doping for semiconductor device with conductive feature

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a source/drain structure, a dielectric layer, a contact plug. The gate structure is positioned over a fin structure. The source/drain structure is positioned in the fin structure and adjacent to the gate structure. The dielectric layer is positioned over the gate structure and the source/drain structure. The contact plug is positioned passing through the dielectric layer. The contact plug includes a first metal compound including one of group III elements, group IV elements, group V elements or a combination thereof.

Semiconductor structure with doped contact plug and method for forming the same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure, disposed over the substrate; a gate structure, disposed over the substrate and covering a portion of the fin structure; a first sidewall, disposed over the substrate and surrounding a lower portion of the gate structure; and a second sidewall, disposed over the first sidewall and directly surrounding an upper portion of the gate structure, wherein the first sidewall is orthogonal to the second sidewall.

Semiconductor structure and method for forming the same

A method for forming a semiconductor device structure is provided. The method includes depositing a gate dielectric layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the gate dielectric layer is over the first fin portion. The method includes forming a gate electrode layer over the gate dielectric layer. The gate electrode layer includes fluorine. The method includes annealing the gate electrode layer and the gate dielectric layer so that fluorine from the gate electrode layer diffuses into the gate dielectric layer.

Method for forming semiconductor device structure having oxide layer

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure protruding from the substrate, the fin structure extending along a first direction; isolation features disposed on both sides of the fin structure; a gate structure over the fin structure and extending on the isolation features along a second direction perpendicular to the first direction; and wherein the gate structure includes a first segment and a second segment, the second segment being over the first segment and including a greater dimension in the first direction than that of the first segment.

Semiconductor structure and method of forming the same

A semiconductor device having a high-k gate dielectric, and a method of manufacture, is provided. A gate dielectric layer is formed over a substrate. An interfacial layer may be interposed between the gate dielectric layer and the substrate. A barrier layer, such as a TiN layer, having a higher concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer is formed. The barrier layer may be formed by depositing, for example, a TiN layer and performing a nitridation process on the TiN layer to increase the concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer. A gate electrode is formed over the barrier layer.

Barrier layer for dielectric layers in  semiconductor devices

A method for manufacturing a semiconductor device is provided including forming one or more fins over a substrate and forming an isolation insulating layer over the one or more fins. A dopant is introduced into the isolation insulating layer. The isolation insulating layer containing the dopant is annealed, and a portion of the oxide layer is removed so as to expose a portion of the fins.

FinFET with doped isolation insulating layer

A FinFET includes a fin structure, a gate, a source-drain region and an inter layer dielectric (ILD). The gate crosses over the fin structure. The source-drain region is in the fin structure. The ILD is laterally adjacent to the gate and includes a dopant, in which a dopant concentration of the ILD adjacent to the gate is lower than a dopant concentration of the ILD away from the gate.

FinFET

A FinFET structure includes a substrate, a plurality of stripes, a metal gate and an oxide material. The stripes are on the substrate. The metal gate is on a sidewall and a top surface of one of the stripes. The oxide material is between the metal gate and the stripes. An average roughness of an interface between the metal gate and the oxide material is in a range of from about 0.1 nm to about 0.2 nm.

FinFet structure

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Wei-Ming You