Faraday Technology Corporation

Pericom Technology (shanghai) Co., Ltd.

Wei-Ming Lin

Hong-Yi Huang

Song-Rong Han

Chia-Liang Lai

Jung-Yu Chang

A clock generating apparatus and a fractional frequency divider thereof are provided. The fractional frequency divider includes a frequency divider (FD), a plurality of samplers, a selector and a control circuit. An input terminal of the FD is coupled to an output terminal of a multi-phase-frequency generating circuit. Input terminals of the samplers are coupled to an output terminal of the FD. Trigger terminals of the samplers receive the sampling clock signals. The input terminals of the selector are coupled to output terminals of the samplers. An output terminal of the selector is coupled to a feedback terminal of the multi-phase-frequency generating circuit. The control circuit provides a fraction code to a control terminal of the selector, so as to control the selector for selectively coupling the output terminal of one of the samplers to the feedback terminal of the multi-phase-frequency generating circuit.

Clock generating apparatus and fractional frequency divider thereof

The present invention provides one pulsewidth control loop (PWCL) device with complementary signals. The PWCL device includes one control stage circuit, one buffer chain, one complementary circuit, two charge pumps, and one comparator. The control stage circuit is used to receive a clock signal and the control signal of the comparator, and output a signal to the buffer chain. The buffer chain is used to receive the output signal from the control stage circuit and output a signal to the complementary circuit. The complementary circuit is used to receive the output signal from the buffer chain and output two complementary signals. Each of the two charge pumps is used to receive one of the output signals from the complementary circuit and output a signal to be one of the inputs of the comparator. The comparator is used to receive the output signals from each of the two charge pumps. Then, the comparator outputs a signal and feedbacks to be one of the input signals of the control stage circuit. The control loop device utilizes the complementary signals to adjust the pulsewidth and increase the stability of the control loop device.

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Taipei, Taiwan

Wei-Ming Lin