Motorola Corporation

Wei-Ming Chen

Kuo-Tung Chang

Craig T Swift

Frank Kelsey Baker, Jr

Ko-Min Chang

Erwin J Prinz

Shih-Wei Sun

Douglas R Roberts

Paul G Tsui

Kevin Yun-kang Wu

Lee Z Wang

Keith Forbes

Gregory M Yeric

In one embodiment, the reliability of an integrated circuit having a floating gate device (50), a high breakdown voltage transistor (52), and a low breakdown voltage transistor (54), which are electrically isolated from each other by a trench isolation region (12), is improved by using an oxidation resistant layer (24). The oxidation resistant layer (24) protects portions of the trench isolation region (12) when the gate dielectric layer (30) for the high breakdown voltage transistor (52) is formed, and when the gate dielectric layer (36) for the low breakdown voltage transistor (54) is formed. The oxidation resistant layer (24) minimizes etching of the field isolation region (12) so that thinning or recessing of the field isolation region (12) is minimized.

Method for forming an integrated circuit

An EEPROM device includes a split-gate FET (10) having a source (36), a drain (22), a select gate (16) adjacent the drain (22), and a control gate (32) adjacent the source (36). When programming the split-gate FET (10), electrons are accelerated in a portion of a channel region (38) between the select gate (16) and the control gate (32), and then injected into a nitride layer (24) of an ONO stack (25) underlying the control gate (32). The split-gate FET (10) is erased by injecting holes from the channel region (38) into the charge nitride layer (24). When reading data from the split-gate FET (10), a reading voltage is applied to the drain (22) adjacent the select gate (16). Data is then read from the split-gate FET (10) by sensing a current flowing in a bit line coupled to the drain (22).

Split-gate memory device and method for accessing the same

A non-volatile memory having a control gate (14) and a sidewall select gate (28) is illustrated. The sidewall select gate (28) is formed in conjunction with a semiconductor doped oxide (20) to form a non-volatile memory cell (7). The semiconductor element used to dope the oxide layer (20) will generally include silicon or germanium. The non-volatile memory cell (7) is programmed by storing electrons in the doped oxide (20), and is erased using band-to-band tunneling.

Method of making and accessing split gate memory device

A metal-semiconductor compound (72, 74, 76) is formed after a step that introduces nitrogen into regions (52, 54, 56) of the device (100). In one embodiment, a nitrogen-containing gas is exposed to surfaces (42, 44, 46) before forming a titanium layer (62) is deposited. A one-step anneal is performed to form titanium disilicide regions (72, 72, 76) that are in the C54 phase without thermal agglomeration or forming electrical shorts between the titanium disilicide regions (72, 74, 76).

Process for forming a semiconductor device having a metal-semiconductor

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Austin, TX, United States of America

Wei-Ming Chen