Taiwan Semiconductor Manufacturing Comp. Ltd.

Wei Min Chan

Yen-Huei Chen

Hung-Jen Liao

Wei-Cheng Wu

Chien-Chen Lin

Shao-Yu Chou

Kao-Cheng Lin

Chen-Lin Yang

Jonathan Tsung-Yung Chang

Ping-Wei Wang

Cheng Hung Lee

Pei-Yuan Li

Shih-Lien Linus Lu

Chih-Yu Lin

Chiting Cheng

Yangsyu Lin

Yu-Hao Hsu

Fu-An Wu

Jung-Ping Yang

Jihi-Yu Lin

Jack Liu

Jui-Feng Kuan

Li-Wen Wang

Chin-Cheng Kuo

Chih-Cheng Yu

Hidehiro Fujiwara

Ken-Hsien Hsieh

Wei-Yi Hu

You-Cheng Xiao

Kmin Hsu

Hsiu-Hui Yang

Shang Lin Wu

Yen Lin Chung

Hau-Tai Shieh

Yi-Tzu Chen

Hsien-Yu Pan

Hsu-Shun Chen

Chia-Che Chung

Chun-Jiun Dai

Chung-Hsien Hua

Yung-Ning Tu

Ping Wang

Chien Hui Huang

Wei-Yu Hu

Kun-hsi Li

Chia-Chi Hung

Hsiang-Yun Lin

A memory device is provided which includes a first memory cell including a first transistor and a second transistor coupled to the first transistor in parallel. Gates of the first transistor and the second transistor are coupled to each other, and the gates of the first transistor and the second transistor pass different layers and overlap with each other. Types of the first transistor and the second transistor are the same.

Memory device

Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.

Multi-stage bit line pre-charge

A memory cell includes a first, second, third, and fourth transistor, a first and a second inverter, and a first and second word line. The first inverter is coupled to the first and third transistor. The second inverter is coupled to the first inverter and the first and third transistor. The first word line is configured to supply a first word line signal, is on a first metal layer above a front-side of a substrate, and is coupled to the first and third transistor. The second word line is configured to supply a second word line signal, and is on a second metal layer below a back-side of the substrate opposite from the front-side of the substrate, and is coupled to the second and fourth transistor. At least the first, second, third or fourth transistor are on the front-side of the substrate.

Integrated circuit, system and method of forming the same

A method of operating a memory device is provided. A clock signal is received. Each clock cycle of the clock signal initiates a write operation or a read operation in a memory device. A power nap period is then determined. The power nap period is compared with a clock cycle period to determine that the power nap period is less than the clock cycle period of the clock signal. A header control signal is generated in response to determining that the power nap period is less than the clock cycle period. The header control signal turns off a header of a component of the memory device.

Disclosed herein are related to memory device including an adaptive word line control circuit. In one aspect, the memory device includes a memory cell and a word line driver coupled to the memory cell through a word line. In one aspect, the memory device includes an adaptive word line control circuit including two or more diodes connected in series, where one of the two or more diodes is coupled to the word line.

Adaptive word line control circuit

A device includes a first power rail for a first power domain and a second power rail for a second power domain. A first circuit block is connected to the first power rail and a second circuit block is connected to the second power rail. The first and second circuit blocks are both connected to a virtual VSS terminal. A footer circuit is connected between the virtual VSS terminal and a ground terminal, and the footer circuit is configured to selectively control a connection between the virtual VSS terminal and the ground terminal.

Shared power footer circuit

Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum voltage signal from among the multiple voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum voltage signal from among the multiple voltage signals to minimize power consumption.

Configurable memory storage system

A static random access memory (SRAM) includes a bit cell including a p-type pass gate, a bit information path connected to the bit cell by the p-type pass gate, and a read multiplexer connected to the bit information path. The read multiplexer includes an n-type transistor configured to selectively couple the bit information path to a sense amplifier.

Static random access memory

A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.

SRAM based authentication circuit

A method of operating a memory device is provide. A clock signal is received. Each clock cycle of the clock signal initiates a write operation or a read operation in a memory device. A power nap period is then determined. The power nap period is compare with a clock cycle period to determine that the power nap period is less that the clock cycle period of the clock signal. A header control signal is generated in response to determining that the power nap period is less than the clock cycle period. The header control signal turns off a header of a component of the memory device.

Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.

A physically unclonable function (PUF) generator includes a first sense amplifier that has a first input terminal configured to receive a signal from a first memory cell of a plurality of memory cells, and a second input terminal configured to receive a signal from a second memory cell of the plurality of memory cells. The first sense amplifier is configured to compare accessing speeds of the first and second memory cells of the plurality of memory cells. Based on the comparison of the accessing speeds, the sense amplifier provides a first output signal for generating a PUF signature. A controller is configured to output an enable signal to the first sense amplifier, which has a first input terminal configured to receive a signal from a bit line of the first memory cell and a second input terminal configured to receive a signal from a bit line of the second memory cell.

Physically unclonable function (PUF) generation

Growing community of inventors

Sindian, Taiwan

Wei Min Chan