Cadence Design Systems, Inc.

Vivante Corporation

Silicon Perspective Corporation

Wei-Lun Kao

Wei-Jin Dai

Mitsuru Igusa

I-Min Liu

Lefan Zhong

Hsi-Chuan Chen

Kit-Lam Cheong

Ping Chao

Jia-Jye Shen

Mathematical functions are computed in a single pipeline performing a polynomial approximation (e.g. a quadratic approximation, or the like) using data tables for RCP, SQRT, EXP or LOG using a single pipeline according and opcodes. SIN and COS are also computed using the pipeline according to the approximation ((&#x2212;1)^IntX)*Sin(&#x3c0;*Min(FracX, 1.0&#x2212;FracX)/Min(FracX, 1.0&#x2212;FracX). A pipeline portion approximates Sin(&#x3c0;*FracX) using tables and interpolation and a subsequent stage multiplies this approximation by FracX. For input arguments of x close 1.0. LOG 2(x&#x2212;1)/(x&#x2212;1) is computed using a first pipeline portion using tables and interpolation and subsequently multiplied by (x&#x2212;1). A DIV operation may also be performed with input arguments scaled up to avoid underflow as needed. Inverse trigonometric functions may be calculated using a pre-processing stage and post processing stage in order to obtain multiple inverse trigonometric functions from a single pipeline.

Systems and methods for computing mathematical functions

An integrated circuit (IC) layout system designs nets for interconnecting cells forming modules of a hierarchical IC design. Each module is defined as having one or more ports through which the nets extend when linking cells forming different modules. The layout system automatically inserts buffers into selected segments of the nets to reduce signal path delays through the nets and assigns the inserted buffers to selected modules. However the layout system inserts buffers only into those net segments for which a buffer insertion would not alter the number of ports any module needs to accommodate the net.

IC layout buffer insertion method

An integrated circuit design includes a description of a net for distributing a signal from a root node to one or more leaf nodes downstream of the root node. Some segments of the net include inverters and some segments branch into other segments. The IC design is processed to determine a maximum number of inverters that can be removed from the net without affecting a logic state of the signal as it arrives at the leaf nodes. For each segment of the net other than segments terminating on root or leaf nodes two corresponding data sets are generated: one data set indicates a maximum number of inverters that may be removed downstream of its corresponding segment without altering the logic state of the signal at any downstream leaf node, and the other data set indicates a maximum number of downstream inverters that may be removed that will alter the logic state of the signal arriving at every downstream leaf node. Each data set points to all data sets corresponding to segments immediately downstream of the data set's corresponding segment, so that the data sets for all segments form a decision tree that may be traversed to determine which inverters must be removed to maximize the number of inverters removed from the net without affecting the logic state of the signal arriving at each leaf node.

Method for identifying removable inverters in an IC design

An IC layout system compiles a hierarchical netlist describing an IC into a database having a separate record for each cell and each module of the IC. Each database record references a cell library entry describing the cell or module and indicates a hierarchical relationship between its corresponding cell or module and other IC cells or modules. The system initially processes the database to reduce the number of cell and module records by combining hierarchically related cells and modules into larger cluster cells. The system then processes the database and cell library to generate a trial layout of the IC which positions highly interconnected cells near one another without regard to the hierarchical nature of the design. The system divides the IC design into separate partitions along hierarchical lines and then develops estimates of the size, shape and position of substrate area needed for each partition based on actual areas in the trial layout occupied by cells forming modules to be assigned to each partition. The system also allocates signal path timing constraints based on calculated path delays within the trial layout. The system thereafter processes the database and cell library to separately lay out each partition.

IC layout system employing a hierarchical database by updating cell library

An integrated circuit (IC) layout system initially modifies a netlist describing an IC as a hierarchy of circuit modules to combine clusters of cells forming selected modules so that they form a smaller number of larger cells. This reduces the number of cells forming the IC, thereby reducing the time the system needs to generate an IC layout. The system then generates a trial layout of the IC described by the modified netlist. Based on the shape and position of the area each module occupies in the trial layout, the system estimates the shape and position of a substrate area each module would require in a layout where module areas did not overlap. The system then divides the IC design into several partitions, each including separate set of the modules forming the IC, and creates a partition plan allocating substrate space to each partition based on the estimated space requirement of each module assigned to that partition. The system also creates a timing budget allocating signal path timing constraints among the partitions based on an timing analysis of signal paths delays in the trial layout. Thereafter the system independently lays out each IC partition so that it satisfies that partition's spatial and timing constraints as indicated by the partition plan and timing budget. The partition layouts are then assembled to form a complete IC layout.

Scalable, partitioning integrated circuit layout system

Disclosed herein is a method for dividing an integrated circuit (IC) design into several circuit partitions, each including one or more circuit modules, and then separately carrying out placement and routing for each circuit partition, with each partition being implemented within a separate area of an IC substrate. The method initially generates a whole-chip trial placement that tends to cluster cells of each circuit module together. An IC substrate floor plan assigning modules to various partitions is prepared, with the size, shape and relative position of each partition being determined by size, shape and relative position of areas of the substrate occupied by those modules in the trial floor plan. A trial routing is also performed with information on which to base a pin assignment plan for each module. A detailed placement and routing process is then independently performed for each partition, with placement and routing of cells within each partition constrained by the floor plan and pin assignment plan.

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Cupertino, CA, United States of America

Wei-Lun Kao