United Microelectronics Corp.

National Cheng-kung University

Realtek Semiconductor Inc.

Wei-lun Huang

Ping-Hung Chiang

Chia-Ling Wang

Chia-Wen Lu

Ta-Wei Chiu

Chun-Chieh Chan

Hsisheng Teng

Wu-chou Su

Hai-wen Chen

Te-fu Yeh

Chung-jen Chung

Chia-Lung Hung

Yung-Ming Lin

Wei-Pang Chung

Chia-fen Lin

I-Ting Chiang

Liang-Che Chen

A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A trench isolation structure is disposed in the substrate between the first device region and the second device region. The trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is coplanar with the second bottom surface.

Semiconductor structure and fabrication method thereof

A manufacturing method of a semiconductor device includes the following steps. A first recess and a second recess are formed in a first region and a second region of a semiconductor substrate, respectively. A bottom surface of the first recess is lower than a bottom surface of the second recess in a vertical direction. A first gate oxide layer and a second gate oxide layer are formed concurrently. At least a portion of the first gate oxide layer is formed in the first recess, and at least a portion of the second gate oxide layer is formed in the second recess. A removing process is performed for removing a part of the second gate oxide layer. A thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer after the removing process.

Manufacturing method of semiconductor device

Semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor, a second transistor, a third transistor, and a plurality of shallow trench isolations. The first transistor is disposed in a medium-voltage region and includes a first plane, a first gate dielectric layer, and a first gate electrode. The second transistor is disposed in a boundary region and includes a second plane, a second gate dielectric layer, and a second gate electrode. The third transistor is disposed in a lower-voltage region and includes a third plane, a third gate dielectric layer, and a third gate electrode. The shallow trench isolations are disposed in the substrate, wherein top surfaces of the shallow trench isolations in the medium-voltage region, the boundary region and the low-voltage region are coplanar with top surfaces of the first gate dielectric layer and the second gate dielectric layer.

Semiconductor device and method of fabricating the same

The invention provides a method for forming a semiconductor structure, which comprises providing a substrate, sequentially a first groove and a second groove are formed in the substrate, the depth of the first groove is different from the depth of the second groove, a first oxide layer is formed in the first groove, a second oxide layer is formed in the second groove, an etching step is performed to remove part of the first oxide layer, a first gate structure is formed on the first oxide layer, and a second gate structure is formed on the second oxide layer.

Semiconductor structure and forming method thereof

A storage device sharing system and a storage device sharing method are provided. The storage device sharing system includes a storage device, a first chip and a second chip. The first chip and the second chip are configured to enter a toggle mode and an arbitration mode. In the toggle mode, the first chip that acts as the master controls the arbitration potential to a first control potential and a second control potential, and communicates with the storage device in response to the arbitration potential being the first control potential, and the second chip that acts as a slave communicates with the storage device in response to the arbitration potential being the second control potential.

Storage device sharing system and storage device sharing method

An image processing chip includes a first interface port, a second interface port, a first upstream facing port (UFP) physical layer module, a first configuration channel detection module, a second upstream facing port (UFP) physical layer module, a second configuration channel detection module, a display signal processing module, a USB signal processing module, an image signal output port and a USB signal output port. The first configuration channel detection module is coupled to the first interface port through a first configuration channel pair, and configured to, after being communicated through a USB specification, detect a first configuration channel signal of a first input signal group to determine a signal type of the first input signal group, and control the first UFP physical layer module to output the first input signal group with a first signal configuration according to the signal type of the first input signal group.

Image processing chip

A semiconductor quantum dot is provided with a non-metallic substrate, and has a particle size ranged from 0.3 to 100 nm. A method of carrying out a chemical reaction or a photoluminescence reaction by using the semiconductor quantum dot is also provided. A redox reaction of a target sample is carried out, an active substance is generated, or an electron-hole pair is produced from the semiconductor quantum dot by providing the semiconductor quantum dot with a predetermined energy. Photons are released by the combination of the electron-hole pair so as to perform the photoluminescence reaction.

Semiconductor quantum dot and method of carrying out chemical reaction or photoluminescence reaction by using the same

A molecular probe includes a detector molecule specific to a target molecule, and at least one label linked covalently or non-covalently to the detector molecule. The label includes a catalyst for generating electrons and/or mediators from a solution. The catalyst includes a nanomaterial, an enzyme, a metal, and/or a metal complex. The mediators can accumulate in the solution for a period of time. The detector molecule and the target molecule interact with each other by a protein based or nucleotide sequence based interaction. The mediators participate in a chemical reaction that generates a signal that may be a change in optical, electromagnetic, thermodynamic or mechanical properties. Generation efficiency of the mediators is enhanced by providing an energy to the solution. The molecular probe may be used with a molecular detection assay performed on a surface. A method for assaying the target molecule using the molecular probe is also provided.

Growing community of inventors

Tainan, Taiwan

Wei-lun Huang