United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

Au Optronics Corporation

National Sun Yat-Sen University of Kaohsiung

Wei-Lun Hsu

Te-Yuan Wu

Wen-Fang Lee

Chih-Chung Wang

Ke-Feng Lin

Hung-Lin Shih

Ching-Ming Lee

Yu-Hsien Lin

Ji-Fu Kung

Shan-Shi Huang

Yan-Hsiu Liu

Ming-Tsung Yeh

Yung-Chien Kung

Am-Tay Luy

Yao-Pi Hsu

Che-Hung Huang

Ming-Tsung Lee

Sung-Nien Tang

Hsu-Yang Wang

Shyan-Liang Chou

Ping-Cheng Hsu

Hsin-Che Huang

Feng-Yi Chang

Chih-Chien Liu

Fu-Che Lee

Shih-Fang Tzou

Bin-Siang Tsai

Yu-Hsiang Hung

Chung-Yi Chiu

Fu-Yu Tsai

Wei-Hsin Liu

Chia-Lung Chang

Ying-Chih Lin

Ming-Te Wei

Gang-Yi Lin

Chih-Jen Huang

Tzu-Chin Wu

Chia-Liang Liao

Shih-Chieh Pu

Chao-Nan Chen

Pi-Hsuan Lai

Shou-Peng Weng

Pao-An Chang

Chao-Yuan Su

Yeo-Wan Chiang

En-Li Lin

Yat-Kai Sun

Cheng-Chia Liu

Shang-Yi Yang

Chia-Chun Kao

Chun-Hsiung Peng

Chung-Ping Chao

An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.

Integrated circuit structure with semiconductor devices and method of fabricating the same

A method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; forming a conductive layer in the trench; forming a metal layer on the conductive layer; forming a mask layer on the metal layer; and patterning the mask layer, the metal layer, and the conductive layer to form a bit line structure.

Semiconductor device and method for fabricating the same

According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; and forming a bit line structure in the trench.

A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.

Method of forming layout definition of semiconductor device

A method for fabricating semiconductor device includes the steps of: forming a bit line structure on a substrate; forming a first spacer, a second spacer, and a third spacer around the bit line structure; forming an interlayer dielectric (ILD) layer on the bit line structure; planarizing part of the ILD layer; removing the ILD layer and the second spacer to form a recess between the first spacer and the third spacer; and forming a liner in the recess.

Semiconductor device including bit line structure of dynamic random access memory (DRAM) and method for fabricating the same

A method, i.e., trapping of structural coloration (TOSC), for fabricating solid 3D network-structured photonic crystals featuring tunable visible structural colorations includes the steps: a PS-PVP copolymer is dissolved in a chloride-containing solvent and is cast as an initial film, the copolymer self-assembles into 3D periodic network-structured morphology; the copolymer in the initial film is swollen in a polar solvent to form a solvated film; the solvated film is dried to form a solid photonic crystal. During evaporation of the polar solvent, the PVP blocks of the copolymer become glassy and form a thin glassy layer on the surface of the solvated film such that the 3D network structures of the copolymer in solvated state can be preserved into the solid photonic crystal revealing the similar periodicity and dimension to that in solvated state, which is very distinct from the film having 1D lamellar structure.

Method for fabricating solid photonic crystals

A method for forming a complementary metal oxide semiconductor device is disclosed. First, a substrate having a first device region and a second device region is provided. A first trench is formed in the first device region and filled with a first material. A second trench is formed in the second device region and filled with a second material. The first material and the second material comprise different stresses. After that, a first gate structure and a second gate structure are formed on the first material and the second material and completely covering the first trench and the second trench, respectively.

Complementary metal oxide semiconductor device and method of forming the same

A method of forming a semiconductor device includes following steps. First of all, plural mandrel patterns are formed on a target layer. Then, plural capping layers are formed to cover a top region and sidewalls of each of the mandrel patterns, respectively. Next, plural spacers are formed at two sides of each of the capping layers, respectively. Following these, a portion of the spacers and the capping layers covered on the top regions of the mandrel patterns are simultaneously removed, and the capping layers is then removed completely.

Method of forming a semiconductor device

A complementary metal oxide semiconductor (CMOS) device is disclosed. The CMOS device includes a substrate with a first device region and a second device region formed thereon. A first isolation structure is formed in the first device region, and includes a first trench filled with a first material. A second isolation structure is formed in the second device region and includes a second trench filled with a second material. The first material and the second material have different stresses. A first gate structure is disposed atop the first material and completely covering the first trench. A second gate structure is disposed atop the second material and completely covering the second trench.

A method of fabricating a semiconductor device is provided. A plurality of sacrificial gates and a plurality of sacrificial gate dielectric layers thereunder are formed on a substrate. An interlayer dielectric layer is filled between the sacrificial gates. A protective layer is formed on the interlayer dielectric layer. The sacrificial gates and the sacrificial gate dielectric layers are removed to form an opening, wherein the interlayer dielectric layer is protected by the protective layer from recessing. A stacked gate structure is formed in the opening, wherein the protective layer is removed.

Method of fabricating semiconductor device

A semiconductor power device is provided, comprising a substrate of a first conductive type, a buffering layer of a second conductive type formed on the substrate, a voltage supporting layer formed on the buffering layer, and alternating sections of different conductive types formed at the substrate. The voltage supporting layer comprises first semiconductor regions of the first conductive type and second semiconductor regions of the second conductive type, wherein the first semiconductor regions and the second semiconductor regions are alternately arranged. The alternating section and the buffering layer form a segmented structure of alternated conductive types, which is used as an anode of the semiconductor device.

Semiconductor power device

The present invention provides a method of fabricating a HV MOS transistor device, including forming a deep well in a substrate, and the deep well; forming a first doped region in the deep well, and the first doped region, wherein a doping concentration of the first doped region and a doping concentration of the deep well in at least one electric field concentration region has a first ratio, the doping concentration of the first doped region and the doping concentration of the deep well outside the electric field concentration region has a second ratio, and the first ratio is greater than the second ratio; and forming a high voltage well in the substrate, and forming a second doped region and a third doped region respectively in the deep well and in the high voltage well.

Method of fabricating high voltage metal-oxide-semiconductor transistor device

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Hsin-Chu Hsien, Taiwan

Wei-Lun Hsu