Taiwan Semiconductor Manufacturing Comp. Ltd.

Asustek Computer Inc.

Acer Laboratories Inc.

Taiwan Semiconducor Manufacturing Company, Ltd.

Wei-Lun Chen

Li-Te S Lin

Chao-Hsien Huang

Pinyen Lin

Tze-Chung Lin

Yen-Ming Chen

Chia-Chien Kuang

Tsung-Yen Yu

Yao-Jen Liu

Guan-De Kuo

Shao-Hsiang Chen

Li-Te Lin

Chin-Chuan Lee

The present disclosure describes a semiconductor device with substantially uniform gate regions and a method for forming the same. The method includes forming a fin structure on a substrate, the fin structure including one or more nanostructures. The method further includes removing a portion of the fin structure to expose an end of the one or more nanostructures and etching the end of the one or more nanostructures with one or more etching cycles. Each etching cycle includes purging the fin structure with hydrogen fluoride (HF), etching the end of the one or more nanostructures with a gas mixture of fluorine (F) and HF, and removing an exhaust gas mixture including an etching byproduct. The method further includes forming an inner spacer in the etched end of the one or more nanostructures.

Method for fabricating a semiconductor device including etching nanostructures

A method for fabricating a semiconductor arrangement includes performing a first etching of a semiconductive structure to expose a first portion of a sidewall of a first layer adjacent the semiconductive structure. The first etching forms a first protective layer on the first portion of the sidewall of the first layer, and the first protective layer is formed from a first accumulation of by-product material formed from an etchant of the first etching interacting with the semiconductive structure. The method includes performing a first flash to remove at least some of the first protective layer.

Semiconductor arrangement and method for making

A semiconductor structure includes: a substrate and a fin protruding from the substrate. The fin comprises a first semiconductive layer over the substrate, a second semiconductive layer over the first semiconductive layer, and a dielectric layer disposed between the first semiconductive layer and the second semiconductive layer and electrically isolated from the first semiconductive layer and the second semiconductive layer. The semiconductor structure further includes a gate electrode including: a first conductive portion extending along two opposite sidewalls of the first semiconductive layer and along an upper surface of the substrate; and a second conductive portion electrically isolated from the first conductive portion and extending along two opposite sidewalls of the second semiconductive layer and along an upper surface of the fin.

Semiconductor structure and method of manufacturing the same

The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.

Semiconductor device with reduced loading effect

A semiconductor device and methods of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure with first and second nanostructured layers on the fin structure, forming a polysilicon structure around the superlattice structure, forming a source/drain opening within the superlattice structure, forming a first conductivity type S/D region within a first portion of the S/D opening, forming an isolation layer on the first conductivity type S/D region and within a second portion of the S/D opening, forming a second conductivity type S/D region on the isolation layer and within a third portion the S/D opening, and replacing the polysilicon structure and the second nanostructured layers with a gate structure that surrounds the first nanostructured layers. Materials of the first and second nanostructured layers are different from each other and the second conductivity type is different from the first conductivity type.

Isolation layers in stacked semiconductor devices

A semiconductor structure includes a substrate and a fin protruding from the substrate along a first direction, wherein the fin includes a first semiconductive layer over the substrate, a second semiconductive layer over the first semiconductive layer along the first direction, and a dielectric layer disposed between the first semiconductive layer and the second semiconductive layer and electrically isolated from the first semiconductive layer and the second semiconductive layer. The semiconductor structure also includes a gate electrode including: a first conductive portion extending in a second direction different from the first direction and including an upper surface level with an upper surface of the first semiconductive layer; and a second conductive portion electrically isolated from the first conductive portion and including a bottom surface level with a bottom surface of the second semiconductive layer.

A semiconductor structure comprises a substrate and a fin extruding from the substrate along a first direction, wherein the fin comprises a first conductive type semiconductive layer over the substrate, a second conductive type semiconductive layer stacking over the first conductive type semiconductive layer along the first direction, and a dielectric layer sandwiched by the first conductive type semiconductive layer and the second conductive type semiconductive layer providing electrical isolation along the first direction between the first conductive type semiconductive layer and the second conductive type semiconductive layer.

An audio processing method includes the following steps: receiving audio information; capturing a square wave signal, a white signal, and a speech signal of the audio information; calculating a loudness value of the audio information; calculating a first sound quality value and a second sound quality value of the audio information by using the square wave signal, the white signal, and the speech signal of the audio information; calculating a sound quality level of the audio information by using a first calculation formula, the first calculation formula being the loudness value*[1+(B*the first sound quality value+C*the second sound quality value)], where B and C are respectively values greater than 0 and less than 0.1; and displaying a value of the sound quality level of the audio information.

Audio processing method and audio processing device

This invention discloses a novel design to solve the clock skew problems in a data processing system by using PLL circuitry inside a memory controller in combination with an adjustable delay element to provide a write clock signal, a read clock signal, and a memory clock signal for triggering the write data buffer and the read buffer of the memory controller, and the memory module respectively. The memory clock signal has a phase lead relative to the read clock signal and a phase lag relative to the write clock signal. The phase lead and the phase lag compensate for phase differences between clock signals arriving at the read data buffer and the write data buffer of the memory controller, and the memory module respectively due to phase delays resulting from the different paths for transmitting clock signals, thereby synchronizing the clock signals.

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Taipei, Taiwan

Wei-Lun Chen