Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Sony Corporation

Texas Instruments Corporation

Wei Lu

Alex See

Huang Liu

Benfu Lin

Liang Choo Hsia

Lei Wang

Xuesong Rao

Alex K H See

Mei Sheng Zhou

Hai Cong

Lup San Leong

Liang Li

Hui Peng Koh

Juan Boon Tan

Hong Yu

Jia Zhen Zheng

Chim Seng Seet

Jong Sung Park

Xiaobing Sun

Jian Zhang

Meisheng Zhou

Luona Goh

Sin Leng Lim

In Ki Kim

Min Hwan Kim

Jeff Jianhui Ye

Shyue Seng Tan

Jin Xu

Lap Chan

Elgin Kiok Quek

Wanbing Yi

John Leonard Sudijono

Jae Gon Lee

Fan Zhang

Yeow Kheng Lim

Johnny Widodo

Yugang Ma

Wuping Liu

Kanzo Okada

Chun Hui Low

Marvin De-Dui Liao

Wei Shao

Benjamin Lee Amey

Bangun Indajang

Yih-Shung Lin

Yoke Leng Lim

Kho Liep Chok

Yung Fu Alfred Chong

Fangyue Liu

Teuta K Williams

Vish Srinivasan

Jianhui Ye

Hao Zhang

Lian Choo Goh

Jack Cheng

Yihua Wang

Martina Damayanti

Jeff Shu

Jyoti Gupta

Loh Nah Luona Goh

Jingze Tian

Luona Goh Loh Nah

Charlie Wee Tay

Methods of forming a semiconductor device are presented. The method includes providing a wafer with top and bottom wafer surfaces. The wafer includes edge and non-edge regions. A dielectric layer having a desired concave top surface is provided on the top wafer surface. The method includes planarizing the dielectric layer to form a planar top surface of the dielectric layer. The desired concave top surface of the dielectric layer thicknesses compensates for different planarizing rates at the edge and non-edge regions of the wafer.

CMP wafer edge control of dielectric

Methods for fabricating integrated circuits having improved active regions are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having an upper surface and including active regions and isolation regions formed in a low voltage device area and in a high voltage device area. The method includes selectively forming voids between the isolation regions and the active regions in the high voltage device area to expose active side surfaces. The method further includes oxidizing the upper surface and the active side surfaces to form a gate oxide layer over the low voltage device area and the high voltage device area.

Methods for fabricating integrated circuits with improved active regions

Devices and methods for forming a device are presented. The method includes providing a substrate having circuit component and a dielectric layer over the substrate. The dielectric layer includes a plurality of inter level dielectric (ILD) layers and the uppermost dielectric layer includes at least one interconnect. A pad dielectric layer is provided over the uppermost ILD layer. A pad interconnect for receiving a wire bond is formed in the pad dielectric layer. The pad interconnect is coupled to the at least one interconnect of the uppermost ILD layer. A top surface of the pad dielectric layer is substantially coplanar with a top surface of the pad interconnect. A passivation layer is formed over the pad dielectric layer.

Planar passivation for pads

A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing.

CMP head structure with retaining ring

A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table; a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes the retaining ring; a sensor for sensing the step height between the retaining ring and its membrane and a controller for adjusting the movement of the retaining ring based on the step height between the retaining ring and its membrane to ensure the step height remains at a fixed value as the retaining ring wears out.

Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes providing a semiconductor device with a metal silicide electrically coupled thereto. A contact opening exposing the metal silicide is formed to the semiconductor device. A conductive material is deposite within the contact opening to form a contact to the metal silicide while simultaneously forming a contact seam void within the contact. A self-aligned conductive material is deposited within the contact to form a conductive plug that at least partially fills the contact seam void, and a metallization layer is deposited overlying the contact.

Methods for fabricating integrated circuits having device contacts

A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.

Through silicon vias

Device and a method of forming a device are presented. The method includes providing a substrate prepared with isolation regions. The substrate includes first, second and third regions. The first region includes a memory region, the second region includes a high voltage (HV) region and the third region includes a logic region. An additional dielectric layer covering the substrate and the isolation regions is formed. A first select region is selectively processed while protecting first non-select regions. The first select region is one of the first, second and third device regions. A first gate dielectric is formed on the select region. Top substrate active area and isolation regions of the first non-select regions are not exposed during processing of the first select region and forming the first gate dielectric.

Isolation for embedded devices

CMP head structure

Integrated circuits with reduced shorting and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing a gap fill dielectric overlying a semiconductor substrate. The gap fill dielectric is formed with an upper surface having a height differential. The method includes reducing the height differential of the upper surface of the gap fill dielectric. Further, the method includes depositing an interlayer dielectric overlying the gap fill dielectric. Also, the method forms an electrical contact to a selected location overlying the semiconductor substrate.

Integrated circuits with improved gap fill dielectric and methods for fabricating same

Methods for forming a device are presented. A substrate having top and bottom pad stacks is provided. Each pad stack includes at least first and second pad layers. The second pad layers of the top and bottom pad stacks include an initial thickness Tand Trespectively. Trench isolation regions are formed in the substrate. The second pad layer of the top and bottom pad stacks are removed after forming the trench isolation regions by a batch wet etch process.

Wafer processing

A stress liner having first and second stress type is provided over a first type and a second type transistor to improve reliability and performance without incurring area penalties or layout deficiencies.

Stress liner for stress engineering

A composite etch stop layer which comprises primary and secondary stop layers is used to form contacts in a dielectric layer to contact regions in a substrate. The secondary etch stop layer includes a high-k dielectric material to achieve high etch selectivity with the dielectric layer during contact formation. The secondary stop layer is removed to expose the contact regions. Removal of the secondary stop layer is achieved with high selectivity to the materials therebelow.

Method of forming high-k dielectric stop layer for contact hole opening

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Singapore, Singapore

Wei Lu