Other

University of Michigan

Crossbar, Inc.

Memryx Incorporated

Electronics and Telecommunications Research Institute

Harvard College

National Science Foundation

Wei Lu

Sung Hyun Jo

Mohammed Zidan

Michael Quoc Lu

Dexi Lu

Chester Liu

Jacob Christopher Botimer

Zhengya Zhang

Jianhong Hu

Hagop A Nazarian

Kuk-Hwan Kim

Timothy Wesley

Fan-hsuan Meng

Timothy Alan Wesley

Fuxi Cai

Patrick Sheridan

Chao Du

Charles M Lieber

Young Jun Kim

Dongwoo Suh

Bogdan I Epureanu

Pingsha Dong

Fengchao Liu

Brian Timko

Limei Xu

Yue Wu

Hao Yan

Bogdan Ioan Popa

Alan Taub

Lin Chen

David Dexi Lu

Jie Xiang

Ganghyeok Im

Ching-Yu Ko

A memory processing unit (MPU) can include a first memory including a plurality of memory regions and a plurality of processing regions. One or more of the plurality of memory regions can be configured in a corresponding pluralities of memory blocks. The memory blocks can be configured to store weights in a selected one of a plurality of bit precisions. The plurality of processing regions can be interleaved between the plurality of regions of the first memory. The processing regions can include a plurality of core groups, wherein the core groups include one or more compute cores.

Core group memory processing with multi-precision weight packing

A processing unit can include a plurality of chiplets coupled in a cascade topology by a plurality of interfaces. A set of the plurality of cascade coupled chiplets can be configured to execute a plurality of layers or blocks of layers of an artificial intelligence model. The set of cascade coupled chiplets can also be configured with parameter data of corresponding ones of the plurality of layers or blocks of layers of the artificial intelligence model.

Chiplet based artificial intelligence accelerators and configuration methods

A memory processing unit (MPU) can include a first memory, a second memory, a plurality of processing regions and control logic. The first memory can include a plurality of regions. The plurality of processing regions can be interleaved between the plurality of regions of the first memory. The processing regions can include a plurality of compute cores. The second memory can be coupled to the plurality of processing regions. The control logic can configure data flow between compute cores of one or more of the processing regions and corresponding adjacent regions of the first memory. The control logic can also configure data flow between the second memory and the compute cores of one or more of the processing regions. The control logic can also configure data flow between compute cores within one or more respective ones of the processing regions. The control logic can also configure array data for storage memory of the MPU.

Memory processing unit core architectures

A battery cell in which a liquid electrolyte is disposed and an acoustic transducer in mechanical communication with the battery cell. The acoustic transducer is configured to generate acoustic waves. The acoustic waves have a wavelength larger than a dimension of the battery cell such that the acoustic waves generate cavitation bubbles in the electrolyte.

Acoustic wave-based battery management

A memory processing unit (MPU) can include a first memory, a second memory, a plurality of processing regions and control logic. The first memory can include a plurality of regions. The plurality of processing regions can be interleaved between the plurality of regions of the first memory. The processing regions can include a plurality of compute cores. The second memory can be coupled to the plurality of processing regions. The control logic can configure data flow between compute cores of one or more of the processing regions and corresponding adjacent regions of the first memory. The control logic can also configure data flow between the second memory and the compute cores of one or more of the processing regions. The control logic can also configure data flow between compute cores within one or more respective ones of the processing regions.

Inter-layer communication techniques for memory processing unit architectures

Techniques for computing matrix convolutions in a plurality of multiply and accumulate units including data reuse of adjacent values. The data reuse can include reading a current value of the first matrix in from memory for concurrent use by the plurality of multiply and accumulate units. The data reuse can also include reading a current value of the second matrix in from memory to a serial shift buffer coupled to the plurality of multiply and accumulate units. The data reuse can also include reading a current value of the second matrix in from memory for concurrent use by the plurality of multiply and accumulate units.

Matrix data reuse techniques in multiply and accumulate units of processing system

A method of joining a first component and a second component that are made of dissimilar metals. In some embodiments, the method comprises applying friction between the first component and the second component sufficient to generate a layer of quasi-liquid metal and produce shear localization within the quasi-liquid metal at a dissimilar metal interface between the first component and the second component and terminating the application of friction at a predetermined time after generation of the quasi-liquid metal. In some embodiments, the method comprises applying amorphous metal between at least a portion of the first component and the second component at a dissimilar metal interface, heating the amorphous metal to a temperature between its glass transition temperature (T) and the lowest melting temperature of the components involved, and applying compression pressure to generate thermoplastic deformation of the amorphous metal.

Methods of joining dissimilar metals without detrimental intermetallic compounds

Memory processing unit architectures and configurations

A matrix multiplication engine can include a plurality of processing elements configured to compute a matrix dot product as a summation of a sequence of vector-vector outer-products.

Matrix multiplication engines

A memory processing unit (MPU) configuration method can include mapping operations of one or more neural network models to sets of cores in a plurality of processing regions. In addition, dataflow of the one or more neural network models can be mapped to the sets of cores in the plurality of processing regions. Furthermore, configuration information can be generated based on the mapping of the operations of the one or more neural network models to the set of cores in the plurality of processing regions and the mapping of dataflow of the one or more neural network models to the sets of cores in the plurality of processing regions. The method can be implemented by generating an initial graph from a neural network model. A mapping graph can then be generated from the final graph. One or more configuration files can then be generated from the mapping graph.

Memory processing unit architecture mapping techniques

Disclosed are a system and methods for preventing dendrite growth in an electrochemical cell through the use of a protective layer. The electrochemical cell may comprise an anode, a cathode, an electrolyte, and a protective layer, wherein the protective layer is capable of producing a voltage. The voltage produced can selectively shield metal ions from certain regions of the protective layer. This shielding can result in a more uniform flux of metal ions being transferred across the electrode-electrolyte interface in subsequent electrodeposition and electrodissolution processes. As a result, an electrode with such a protective layer can exhibit improved performance and durability, including markedly lower overpotentials and largely improved metal (e.g., lithium) retention.

Dendrite-free lithium metal battery by deformation-induced potential shielding

An in-memory computing system for computing vector-matrix multiplications includes an array of resistive memory devices arranged in columns and rows, such that resistive memory devices in each row of the array are interconnected by a respective word line and resistive memory devices in each column of the array are interconnected by a respective bitline. The in-memory computing system also includes an interface circuit electrically coupled to each bitline of the array of resistive memory devices and computes the vector-matrix multiplication between an input vector applied to a given set of word lines and data values stored in the array. For each bitline, the interface circuit receives an output in response to the input being applied to the given wordline, compares the output to a threshold, and increments a count maintained for each bitline when the output exceeds the threshold. The count for a given bitline represents a dot-product.

Memory processing unit

A monolithic integrated circuit (IC) including one or more compute circuitry, one or more non-volatile memory circuits, one or more communication channels and one or more communication interface. The one or more communication channels can communicatively couple the one or more compute circuitry, the one or more non-volatile memory circuits and the one or more communication interface together. The one or more communication interfaces can communicatively couple one or more circuits of the monolithic integrated circuit to one or more circuits external to the monolithic integrated circuit.

Non-volatile memory based processors and dataflow techniques

A memory processing unit architecture can include a plurality of memory regions and a plurality of processing regions interleaved between the plurality of memory regions. The plurality of processing regions can be configured to perform computation functions of a model such as an artificial neural network. Data can be transferred between the computation functions in respective memory processing regions. In addition, the memory regions can be utilized to transfer data between a computation function in one processing region and a computation function in another processing region adjacent to the given memory region.

Memory processing unit architecture

A memory processing unit can be configured to compute partial products between one or more elements of a first matrix stored in a given row of a memory cell array and sequential bits of one or more elements of a second matrix. The partial products can be calculated first sequentially across the set of rows and second sequentially across the bit positions of the elements of the second matrix. Alternatively, the partial products can be calculated first sequentially across the bit positions of the elements of the second matrix first and second sequentially across the set of rows. The partial products for each column of elements can be accumulated and bit shifted to compute the dot product of the first and second matrix.

Memory processing units and methods of computing dot products

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Ann Arbor, MI, United States of America

Wei Lu