Taiwan Semiconductor Manufacturing Comp. Ltd.

Wei-Long Wang

Ru-Gun Liu

Tsai-Sheng Gau

Wen-Chun Huang

Ming-Hui Chih

Ken-Hsien Hsieh

Yung-Sung Yen

Wen-Ju Preet Yang

Gwan Sin Chang

Pi-Tsung Chen

Shih-Ming Chang

Jeng-Horng Chen

Shy-Jay Lin

Cheng-Cheng Kuo

Chien-Hsun Chen

Chia-Ping Chiang

Yu-Po Tang

Cheng-Lung Tsai

Cheng-Kun Tsai

Jeng-Shiun Ho

Faruk Krecinic

Bing-Syun Yeh

Josh J H Feng

Tuane Ying Fang

A method includes determining one or more potential merges corresponding to a color set Aand a color set Aof N color sets, represented by Ato A, used in coloring polygons of a layout of an integrated circuit. N is a positive integer, i and j are integers from 1 to N, and i&#x2260;j. One or more potential cuts corresponding to the color set Aand the second color set Aare determined. An index Ais determined according to the one or more potential merges and the one or more potential cuts. A plurality of parameters F related to the index Ais obtained based on various values of indices fand f. A parameter F is selected among the plurality of parameters F based on a definition of the index A.

Method of merging color sets of layout

Various embodiments of the invention provide techniques to ensure a layout for an integrated circuit is split-able. In a method embodiment, a layout is generated in a customer site having a layout library as inputs wherein the library provides exemplary layouts that have been verified to be spit-able and that can be used and layouts that can cause conflicts to avoid. A real-time odd cycle checker is also provided in which the checker identifies in real time conflict areas and odd cycles as they arise during layout generation. To reduce memory usage layouts of various devices may be separated so that each individual layout or a small number of layouts, rather than a large layout for the whole application circuit, can be checked against conflicts. Once the layout is ready at the customer site, it is sent to the foundry site to be decomposed into two masks and taped-out. Other embodiments are also disclosed.

Decomposing integrated circuit layout

The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.

Dissection splitting with optical proximity correction and mask rule check enforcement

A direct-write system is provided which includes a stage for holding a substrate, a processing module for processing pattern data and generating instructions associated with the pattern data, and an exposure module that includes beams that are focused onto the substrate and a beam controller that controls the beams in accordance with the instructions. The processing module includes vertex pair processors each having bit inverters. Each vertex pair processor is operable to process a respective vertex pair of an input scan line to generate an output scan line. Each bit inverter is operable to invert a respective input bit of the input scan line to generate a respective output bit of the output scan line if a bit position is located between the respective vertex pair, otherwise the respective input bit is copied to the respective output bit. The instructions correspond to the output bits for each beam.

System and method for generating direct-write pattern

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Hsinchu, Taiwan

Wei-Long Wang