Advanced Micro Devices Corporation

Wei Long

Qi Xiang

Yowjuang William Liu

Ming-Ren Lin

Chun Jiang

Michael Lee

Don Wollesen

Scott Allan Bell

Olov B Karlsson

Zicheng Gary Ling

Carl Robert Huster

Concetta E Riccobene

Bill Yowjuang Liu

A semiconductor device includes a wafer having a semiconductor layer with source, body and drain regions. A electrically-conducting region of the semiconductor region overlaps and electrically couples the source region and the body region. The electrical coupling of the source and body regions reduces floating body effects in the semiconductor device. A method of constructing the semiconductor device utilizes spacers, masking, and/or tilted implantation to form an source-body electrically-conducting region that overlaps the source and body regions of the semiconductor layer, and a drain electrically-conducting region that is within the drain region of the semiconductor layer.

Semiconductor-on-insulator body-source contact and method

A field effect transistor (FET) structure, and method for making the same, which further suppresses short-channel effects based on variations within the gate dielectric itself. The FET structure utilizes non-uniform gate dielectrics to alter the vertical electric field presented along the channel. The thickness and/or dielectric constant of the gate dielectric is varied along the length of the channel to present a vertical electric field which varies in a manner that tends to reduce the short-channel effects and gate capacitances.

Non-uniform gate/dielectric field effect transistor

In a system for determining thermal resistance of a field effect transistor, a p-n junction is formed with one of drain and source regions of the transistor for determining a current versus temperature characteristic of the p-n junction. A respective temperature of the transistor is determined for each of a plurality of power dissipation levels through the transistor from the current versus temperature characteristic of the p-n junction. The thermal resistance is a rate of change of the temperature with respect to a rate of change of the power dissipation level for the field effect transistor.

Determination of thermal resistance for field effect transistor formed in SOI technology

Semiconductor-on-insulator body-source contact using shallow-doped source, and method

A fully-depleted semiconductor-on-insulator (SOI) transistor device has an SOI substrate with a buried insulator layer having a nonuniform depth relative to a top surface of the substrate, the buried insulator layer having a shallow portion closer to the top surface than deep portions of the layer. A gate is formed on a thin semiconductor layer between the top surface and the shallow portion of the insulator layer. Source and drain regions are formed on either side of the gate, the source and drain regions each being atop one of the deep portions of the buried insulator layer. The source and drain regions thereby have a greater thickness than the thin semiconductor layer. Thick silicide regions formed in the source and drain regions have low parasitic resistance. A method of making the transistor device includes forming a dummy gate structure on an SOI substrate, and using the dummy gate structure to control the depth of an implantation to form the nonuniform depth buried insulator layer.

Semiconductor-on-insulator transistor with recessed source and drain

The thermal resistance R parameter is determined for a field effect transistor formed with a semiconductor film on a buried insulating material in SOI (semiconductor on insulator) technology. A p-n junction is formed with one of a drain region or a source region of the field effect transistor. The p-n junction is biased at a bias voltage. The p-n junction is heated to a plurality of temperatures. A current conducted through the p-n junction is measured at each of the plurality of temperatures of the p-n junction to generate a current versus temperature characteristic for the p-n junction. A respective current flowing through the p-n junction is measured as the field effect transistor is biased to dissipate each of a plurality of power dissipation levels and with the p-n junction being biased at the bias voltage. The respective temperature of the p-n junction is determined from the measured respective current and the current versus temperature characteristic for each of the plurality of power dissipation levels. The thermal resistance is determined to be a rate of change of temperature with respect to a rate of change of power dissipation level.

STI (Shallow Trench Isolation) structures are fabricated such that leakage current is minimized through a field effect transistor fabricated between the STI structures. The shallow trench isolation structure include a pair of isolation trenches, with each isolation trench being etched through a semiconductor substrate. A first dielectric material fills the pair of isolation trenches and extends from the isolation trenches such that sidewalls of the first dielectric material filling the isolation trenches are exposed beyond the top of the semiconductor substrate. A second dielectric material is deposited on the sidewalls of the first dielectric material exposed beyond the top of the semiconductor substrate. The second dielectric material has a different etch rate in an acidic solution from the first dielectric material filling the isolation trenches. The present invention may be used to particular advantage when the first dielectric material filling up the isolation trenches is comprised of silicon dioxide, and when the second dielectric material deposited on the sidewalls of the first dielectric material is comprised of silicon nitride. With the protective silicon nitride covering the sidewalls of the silicon dioxide filling the STI (shallow trench isolation) trenches, formation of divots is avoided in the silicon dioxide filling the STI (shallow trench isolation) trenches. Thus, when a field effect transistor is fabricated between such STI structures, silicides formed near the STI structures do not extend down toward the junction of the drain contact region and the source contact region of the field effect transistor such that drain and source leakage current is minimized.

STI (Shallow Trench Isolation) structures for minimizing leakage current through drain and source silicides

An integrated circuit (IC) including an integral, high k dielectric de-coupling capacitor constructed using a single conductive layer within the IC structure. The IC comprises a substrate, a dielectric layer disposed over the substrate, and a conductive layer disposed over the dielectric layer. The conductive layer includes a first line disposed adjacent to a second line, and a high k dielectric material disposed between the first line and the second line. The capacitor is formed between the first line and the second line separated by the high k dielectric material. The capacitor is connected by coupling the first line to a signal and coupling the second line to a capacitor signal.

High K dielectric de-coupling capacitor embedded in backend interconnect

A method of reducing the gate resistance in a semiconductor device forms a gate in the semiconductor device followed by the creation of a silicide region on top of the gate. During the initial formation of the silicide region on the gate, formation of silicide on source/drain areas of the semiconductor device is prevented by a shielding material. The shielding material is then removed and additional silicide is created, forming silicide regions on the source/drains and increasing the thickness of the silicide over the gate, thereby lowering the gate resistance.

Dual silicide process to reduce gate resistance

Semiconductor-on-insulator body-source contact using additional drain-side spacer, and method

An integrated circuit (IC) including integral, high k dielectric de-coupling capacitor constructed using a damascene process and contained within a single conductive layer of the IC structure. The IC comprises a substrate, a dielectric layer disposed over the substrate, and a conductive layer disposed over the dielectric layer. The conductive layer includes a first line disposed adjacent to a second line, and a high k dielectric material disposed between the first line and the second line. The capacitor is formed between the first line and the second line separated by the high k dielectric material. Coupling the first line to a signal and coupling the second line to a capacitor signal connects the capacitor.

High k interconnect de-coupling capacitor with damascene process

The gate structure of the MOSFET of the present invention is formed to have a longer length toward the top of the gate structure such that a spacer having a substantially rectangular shaped is formed at the sidewalls of the gate structure. For fabricating a gate structure of a field effect transistor on a semiconductor substrate, a layer of gate structure material is deposited on the semiconductor substrate. The composition of the layer of gate structure material is adjusted along a depth of the layer of gate structure material for a slower etch rate toward a top of the layer of gate structure material that is further from the semiconductor substrate. The gate structure is then formed by patterning and etching the layer of gate structure material. The slower etch rate toward the top of the layer of gate structure material results in a longer length toward a top of the gate structure that is further from the semiconductor substrate. Spacer dielectric is deposited conformally on exposed surfaces of the gate structure. The spacer dielectric is anisotropically etched such that the spacer dielectric remains on sidewalls of the gate structure. The longer length toward the top of the gate structure results in a substantially rectangular shaped spacer dielectric remaining on the sidewalls of the gate structure. The present invention may be used to particular advantage when the gate structure and the spacer having the rectangular shape are formed as part of a field effect transistor such as a MOSFET.

Fabrication of a gate structures having a longer length toward the top for formation of a rectangular shaped spacer

A method for extracting a channel length between a source and a drain in a substrate of a transistor is disclosed herein. The method includes forward biasing the source with respect to the substrate to inject a charge into the substrate, collecting the charge at the drain, and calculating the channel length from the charge collected at the drain.

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Sunnyvale, CA, United States of America

Wei Long