Yangtze Memory Technologies Co., Ltd.

Globalfoundries Singapore Pte. Ltd.

Huawei Technologies Co., Limited

Other

Wuhan Tianma Micro-electronics Co., Ltd

Wuhan Tianma Microelectronics Co., Ltd. Shanghai Branch

Asm Technology Singapore Pte Ltd

Agency for Science, Technology and Research

Southeast University

Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.

Nanyang Technological University

Crrc Yangtze Co., Ltd.

Huazhong University of Science and Technology

Shaanxi University of Science and Technology

China Three Gorges University

Wei Liu

Liang Chen

Zhiliang Xia

Wenxi Zhou

Yanhong Wang

Yuancheng Yang

Cheng Gan

Kun Zhang

Juan Boon Tan

Lei Xue

Hongbin Zhu

Shiqi Huang

Xingyao Zhou

Shi Qi Huang

Ning Jiang

Yana Gao

Kang Yang

Shunqiang Gong

Siping Hu

Bater Chelon

Qijun Yao

Wanbing Yi

Wenyu Hua

Soo Jin Chua

Weihong Xiao

Yeow Kheng Lim

Wei Gu

Kheng Chok Tee

Yam Mo Wong

Ziqun Hua

Hilmi Volkan Demir

Dingjiu Daojian

Wei Shao

Yanwei Shi

Swee Tiam Tan

Guannan Lou

Chao Sun

Hui Luo

Lijie Su

Hao Tang

Zongliang Huo

Lin Y Yang

Jung Min Kim

Chengyuan Liang

Joon Ho Lee

Peng Zhang

Fei Chen

Han Li

Fan Zhang

Qingguo Xie

Shijian Yuan

Shuai Zhang

Soh Yun Siah

Hai Cong

Ka Shing Kenny Kwan

Bei Chao Zhang

Lin Zhang

Simon Shi-Ning Yang

Dong Kyun Sohn

Yuqiang Wang

Yi Wang

Qibing Wei

Wuping Liu

Lei Wang

Peng Yi

Tai-Shung Chung

Xuechuan Wang

Pei Yu

Jian Kuang

Yewei Sun

Danni Tian

Peng Li

Minyi Jia

Shunjun Ding

Gaoxiao Zhang

Huichao Dai

Yi-Yan Yang

Jing Zhou

Yingying Wu

Hui Wang

Liyun Ou

Fengwei Liu

Xiaolong Wang

Wu Liu

Yuanyuan Sun

Jun Xiang

Sheng Su

Yexi Sun

Song Hu

Jun Xu

Ying Li

Yuanwu Wang

Peng Xiao

Chuqiang Tang

Xiaowei Sun

Liangcai Lin

Zhenqing Zhao

Ming Chen

Yi Bin Wang

Suyang Zhou

A display device including a display panel having a display area. The display panel includes pixel circuits located in the display area. Each pixel circuit includes a driving transistor and a voltage regulating module that is configured to adjust a node voltage of the driving transistor by a voltage provided by one voltage regulating signal line of voltage regulating signal lines. The pixel circuits have data refresh frequencies including first and second frequencies. The first frequency is greater than the second frequency. When one pixel circuit performs data refreshing at the first frequency, one voltage regulating signal line is configured to provide a first voltage, and when one pixel circuit performs data refreshing at the second frequency, one voltage regulating signal line is configured to provide a second voltage not equal to the first voltage.

Display device and method for driving display panel

Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a first semiconductor assembly, a second semiconductor assembly, and an inter-assembly bonding layer between the first semiconductor assembly and the second semiconductor assembly. The first semiconductor assembly includes a first array structure and a first periphery structure. The first array structure includes a first memory stack having a plurality of interleaved stack conductive layers and stack dielectric layers. The first periphery structure includes a plurality of first peripheral circuits electrically connected to the first memory stack. The second semiconductor assembly includes a second array structure and a second periphery structure. The second array structure includes a second memory stack having a plurality of interleaved stack conductive layers and stack dielectric layers. The second periphery structure includes a plurality of second peripheral circuits electrically connected to the second memory stack.

Three-dimensional memory devices having semiconductor assemblies bonded by bonding layer and methods for forming the same

The present disclosure relates to a three-dimensional (3D) memory and a fabrication method thereof. The method includes forming a memory chip on a first substrate, disposing a first semiconductor layer on the memory chip, forming a plurality of first contacts through the first semiconductor layer, forming a first peripheral circuit chip based on the first semiconductor layer, disposing a second semiconductor layer on the first peripheral circuit chip, forming a plurality of second contacts through the second semiconductor layer, and forming a second peripheral circuit chip based on the second semiconductor layer. The first peripheral circuit chip is electrically connected with the memory chip through the plurality of first contacts, and the second peripheral circuit chip is electrically connected with the memory chip through the plurality of first and second contacts.

Three-dimensional memory and fabrication method thereof

In certain aspects, a semiconductor device includes a substrate, a first trench isolation in the substrate, a second trench isolation in the substrate and surrounding a portion of the substrate, and a first routing electrode layer extending through the first trench isolation. The portion of the substrate is an active region of a transistor.

Semiconductor devices, systems, and methods for forming the same

A method for forming a three-dimensional (3D) memory device is disclosed. An array of NAND memory strings is formed on a first substrate. A first semiconductor layer is formed above the array of NAND memory strings. The first semiconductor layer includes single crystalline silicon. A first transistor is formed on the first semiconductor layer. A second semiconductor layer is formed above the first transistor. The second semiconductor layer includes single crystalline silicon. A second transistor is formed on the second semiconductor layer.

Methods for forming three-dimensional memory devices

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells, and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. The vertical transistor includes a semiconductor body extending in the first direction, and a gate structure in contact with a plurality of sides of the semiconductor body. One end of the semiconductor body coupled to the storage unit is flush with the gate structure. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. The array of memory cells is coupled to the peripheral circuit across the bonding interface.

Memory devices having vertical transistors and methods for forming the same

In certain aspects, a memory device includes a memory cell including a vertical transistor, and a storage unit having a first end coupled to a first terminal of the vertical transistor. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The memory device also includes a metal bit line coupled to a second terminal of the vertical transistor via an ohmic contact and extending in a second direction perpendicular to the first direction. The memory device further includes a dielectric layer opposing the memory cell with the metal bit line positioned between the dielectric layer and the memory cell. The memory device further includes a conductor extending from the dielectric layer to couple to a second end of the storage unit.

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes a first array of memory cells. The third semiconductor structure includes a second array of memory cells. Each of the memory cells of the first and second arrays includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. The first array of memory cells is coupled to the peripheral circuit across the first bonding interface. The second array of memory cells is coupled to the peripheral circuit across the first bonding interface and the second bonding interfaces.

A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an etch stop structure in a first wafer, forming a first through contact in contact with the etch stop structure, bonding the first wafer to a second wafer to electrically connect the first through contact to a CMOS device of the second wafer, and forming a through substrate contact penetrating a first substrate of the first wafer and the etch stop structure, and in electrically contact with the CMOS device through the first through contact.

Three-dimensional memory devices and fabricating methods thereof

Embodiments of a three-dimensional capacitor for a memory device and fabrication methods are disclosed. The method includes forming, on a first side of a first substrate, a peripheral circuitry having a plurality of peripheral devices, a first interconnect layer, a deep well and a first capacitor electrode. The method also includes forming, on a second substrate, a memory array having a plurality of memory cells and a second interconnect layer, and bonding the first interconnect layer of the peripheral circuitry with the second interconnect layer of the memory array. The method further includes forming, on a second side of the first substrate, one or more trenches inside the deep well, disposing a capacitor dielectric layer on sidewalls of the one or more trenches, and forming capacitor contacts on sidewalls of the capacitor dielectric layer inside the one or more trenches.

Structure and method for forming capacitors for a three-dimensional NAND

A three-dimensional (3D) memory device includes a plurality of memory stacks arranged along a first direction, and a dummy block structure disposed between two adjacent memory stacks. Each memory stack includes a plurality of first conductive layers and a plurality of first dielectric layers alternately stacked along a second direction perpendicular to the first direction. A channel structure extends through the plurality of first conductive layers and the plurality of first dielectric layers along the second direction. A first isolation structure is disposed between the dummy block structure and one of the plurality of memory stacks. A substrate is disposed under the plurality of memory stacks, the dummy block structure, and the first isolation structure. A second isolation structure is disposed in the substrate extending along the second direction.

Three-dimensional memory device and method for forming the same

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second peripheral circuit. The polysilicon layer is between the first semiconductor layer and the second semiconductor layer.

Three-dimensional memory devices and methods for forming the same

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells. The second semiconductor structure includes a first peripheral circuit of the array of memory cells. The first peripheral circuit includes a first transistor. The first semiconductor structure or the second semiconductor structure further includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor. The first peripheral circuit and the second peripheral circuit are stacked over one another.

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. Two adjacent vertical transistors of the vertical transistors in the second direction are mirror-symmetric to one another. The array of memory cells is coupled to the peripheral circuit across the bonding interface.

A single-fiber bidirectional optical transmission apparatus, a wavelength division multiplexing device, and an optical transmission system, is disclosed. The single-fiber bidirectional optical transmission apparatus includes: a first single-light-source coherent optical transceiver, configured to: receive a first optical signal from a first multiplexer/demultiplexer, convert the first optical signal into a first electrical signal, and send the first electrical signal to a first client signal processing apparatus; and a second single-light-source coherent optical transceiver, configured to: receive a second electrical signal from the first client signal processing apparatus, convert the second electrical signal into a second optical signal, and send the second optical signal to the first multiplexer/demultiplexer. A wavelength of the second optical signal is different from a wavelength of the first optical signal.

Single-fiber bidirectional optical transmission apparatus, wavelength division multiplexing device, and optical transmission system

Growing community of inventors

Wuhan, China

Wei Liu