Taiwan Semiconductor Manufacturing Comp. Ltd.

Mstar Semiconductor, Inc.

Industrial Technology Research Institute

Kingpak Technology Inc.

Globalfoundries Singapore Pte. Ltd.

Grade Upon Technology Corporation

Wei Ling Chang

Chen-Hua Douglas Yu

Chuei-Tang Wang

Chieh-Yen Chen

Tin-Hao Kuo

Che-Wei Hsu

Chung Hsien Hsin

Fong-yuan Chang

Chien-Sheng Chen

Feng-Jian Chou

Chih-Yuan Hsieh

Figo Hsieh

Chin-Lu Huang

Chun-Hui Ku

Eng Huat Toh

Shyue Seng Tan

Desmond Jia Jun Loy

Heng-Chih Lin

Hsiu Wen Tu

Henry Tin-Hang Yung

Mon Nan Ho

Chen Pin Peng

Chii-Yah Yuan

Chien-Hsing Lin

Hsu-Hung Chang

Tony Wang

Worrell Tsai

Chun-Te Yu

Ming-Li Wang

Jason Chuang

Chi-Han Lan

I-Shinn Tien

Yung-Chih Lo

Jun Jie Yen

Tun-Nien Hsu

Hai-Chiao Sun

Sheng-Feng Liu

Shiuan-I Shau

Tai-Yu Fang

Shu-Ling Chang

In an embodiment, a device includes: a processor die including circuit blocks, the circuit blocks including active devices of a first technology node; a power gating die including power semiconductor devices of a second technology node, the second technology node larger than the first technology node; and a first redistribution structure including first metallization patterns, the first metallization patterns including power supply source lines and power supply ground lines, where a first subset of the circuit blocks is electrically coupled to the power supply source lines and the power supply ground lines through the power semiconductor devices, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source lines and the power supply ground lines.

Integrated circuit package and method

In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.

In an embodiment, a device includes: a first die array including first integrated circuit dies, orientations of the first integrated circuit dies alternating along rows and columns of the first die array; a first dielectric layer surrounding the first integrated circuit dies, surfaces of the first dielectric layer and the first integrated circuit dies being planar; a second die array including second integrated circuit dies on the first dielectric layer and the first integrated circuit dies, orientations of the second integrated circuit dies alternating along rows and columns of the second die array, front sides of the second integrated circuit dies being bonded to front sides of the first integrated circuit dies by metal-to-metal bonds and by dielectric-to-dielectric bonds; and a second dielectric layer surrounding the second integrated circuit dies, surfaces of the second dielectric layer and the second integrated circuit dies being planar.

Systems, devices and methods of manufacturing a system on silicon wafer (SoSW) device and package are described herein. A plurality of functional dies is formed in a silicon wafer. Different sets of masks are used to form different types of the functional dies in the silicon wafer. A first redistribution structure is formed over the silicon wafer and provides local interconnects between adjacent dies of the same type and/or of different types. A second redistribution structure may be formed over the first redistribution layer and provides semi-global and/or global interconnects between non-adjacent dies of the same type and/or of different types. An optional backside redistribution structure may be formed over a second side of the silicon wafer opposite the first redistribution layer. The optional backside redistribution structure may provide backside interconnects between functional dies of different types.

System, device and methods of manufacture

In an embodiment, a method includes forming a device layer over a first substrate; forming a first interconnect structure over a front-side of the device layer; attaching a second substrate to the first interconnect structure; forming a second interconnect structure over a back-side of the device layer, the second interconnect structure comprising back-side memory elements, wherein the back-side memory elements and a first plurality of active devices of the device layer provide a first memory array; and forming conductive connectors over the second interconnect structure.

Integrated circuit package and method of forming same

The present disclosure generally relates to semiconductor devices, and more particularly, to semiconductor devices having memory cells for multi-bit programming and methods of forming the same. The present disclosure also relates to a method of forming such semiconductor devices. The disclosed semiconductor devices may achieve a smaller cell size as compared to conventional devices, and therefore increases the packing density of the disclosed devices.

Semiconductor devices with memory cells

A factory management system and control system are provided. The factory management system includes: a machine; multiple sensors disposed corresponding to the machine and generates multiple first sensing data; a server; and a control system coupled to the machine and the server. The control system receives the first sensing data to generate multiple corresponding control commands in real time and transmits the control commands to the machine. The control system receives a user login message and receives multiple second sensing data and displays the second sensing data in a user login status. The control system receives a user control command and transmits a second control command corresponding to the user control command to the machine. When the control system determines that an abnormal condition occurs according to the second sensing data in the user login status, the control system sends a warning message.

Factory management system and control system

In an embodiment, a structure includes: a graphics processor device; a passive device coupled to the graphics processor device, the passive device being directly face-to-face bonded to the graphics processor device; a shared memory device coupled to the graphics processor device, the shared memory device being directly face-to-face bonded to the graphics processor device; a central processor device coupled to the shared memory device, the central processor device being directly back-to-back bonded to the shared memory device, the central processor device and the graphics processor device each having active devices of a smaller technology node than the shared memory device; and a redistribution structure coupled to the central processor device, the shared memory device, the passive device, and the graphics processor device.

An RFID tag including a transmitting/receiving unit, a memory and a control unit. A first identification code, a second identification code, a password, and a set of data are stored in the memory. If the set of data is under protection, the set of data is accessible only when a verification procedure corresponding to the password is successfully performed. If the transmitting/receiving unit receives a request for accessing the second identification code, the control unit shall check whether the request includes the first identification code. As long as the checking result of the control unit is yes, even if the set of data is under protection and the verification procedure fails or the verification procedure is not successfully performed, the control unit shall still transmit the second identification code via the transmitting/receiving unit.

RFID tag, operating method of RFID tag and operating method between RFID tag and RFID reader

Growing community of inventors

Hsinchu, Taiwan

Wei Ling Chang