Taiwan Semiconductor Manufacturing Comp. Ltd.

Wei-Lin Chang

Feng-Jia Shiu

Ching-Sen Kuo

Chun-Chang Chen

Sz-Fan Chen

Chihy-Yuan Cheng

Chen-Ming Huang

Po-Wei Liu

Wen-Tuo Huang

Hung-Ling Shih

Yu-Ling Hsu

Shih-Hsien Chen

Shun-Shing Yang

Chia-Sheng Lin

Yu-Chun Chang

ShihKuang Yang

Yu-Hsiang Yang

Chun-Chang Wu

Chih-Chien Wang

Chien-Hung Lin

Chien-hung Lin

A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

ONON sidewall structure for memory device and method for making the same

Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.

Method for reducing charging of semiconductor wafers

ONON sidewall structure for memory device and methods of making the same

A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer.

Improving surface topography by forming spacer-like components

Surface topography by forming spacer-like components

Growing community of inventors

Hsinchu, Taiwan

Wei-Lin Chang