Nan Ya Technology Corporation

Wei-Li Liu

Chuan-Jen Chang

Shu-Liang Nin

Ming-Shiang Wang

A delay line includes at least one delay cell, wherein the delay line utilizes at least one of the at least one delay cell to delay an input signal for generating an output signal, and the at least one delay cell is implemented by a Pseudo NMOS transistor. In addition, a memory control circuit includes a delay locked loop (DLL) having at least one delay cell. The delay locked loop utilizes at least one of the at least one delay cell to delay an input signal for generating an output signal, and the at least one delay cell is implemented by a Pseudo NMOS transistor.

Delay line and memory control circuit utilizing the delay line

A memory access control method is provided. By decoding a read-write command, a mode register set (MRS) signal is generated. When the MRS signal is enabled, a latch outputs a bank-select signal. The bank-select signal is then decoded to generate a register-select signal. Then, an address signal is written into a register selected by the register-select signal. The value of a certain register can be used to determine whether to enable the error check function. Thus, the next generation memory structure with the CRC function can be compatible with the conventional memory structure.

Method for controlling access of a memory

A cyclic redundancy check (CRC) is used for improving error check coverage during memory access. In memory reading process, a part of read data is outputted from the memory via a CRC bus, and a CRC result and the other part of the read data are outputted from the memory via a data bus.

Method for controlling memory access

A semiconductor includes a first sensor amplifier, a second sensor amplifier, a first switch and a second switch. The first sensor amplifier is coupled between a local data line and a memory unit to amplify signals of the memory unit. The second sensor amplifier is coupled to a middle data line to amplify signals of the middle data line. The first switch is coupled between the middle data line and the local data line to equalize voltage levels between the middle data line and the local data line by turning on the first switch according to a data control signal. The second switch is coupled between the local data line and a reference voltage to equalize the local data line to the voltage level of the reference voltage by turning on the second switch according to a local data control signal.

Semiconductor device

In a delay locked loop, a phase detector compares the phases of an input signal and an output signal; a delay line delays the input signal, wherein the delay line includes a plurality of unit delay elements connected in series and the value of the unit delay of each of the unit delay elements is adjusted by a control signal; a multiplexer selects a number of delay stages of the unit delay elements according to the phase comparison result and generates the output signal. The control signal is related to a clock information signal. When the input signal is high frequency, the value of the unit delay would be small; and when the input signal is low frequency, the value of the unit delay would be large.

Delay locked loop

A memory and an operation method thereof are provided. The present invention divides memory banks of the memory into a plurality of memory groups, wherein each memory group has an independent driving power for providing an operating voltage to the corresponding memory bank in the memory group. The present invention specifies two tRRD times which are an inter-group interval and an intra-group interval. The intra-group interval is the minimum time interval between selecting one row of memory banks in a memory group to selecting another row in the memory banks of the same memory group and the inter-group interval is the minimum time interval between selecting one row of the memory banks in one memory group to selecting another row in a different memory group. Further, the inter-group interval is shorter than or equal to the intra-group interval.

Growing community of inventors

Taipei County, Taiwan

Wei-Li Liu