Au Optronics Corporation

Auo Corporation

Au Potronics Corp.

Wei-Li Lin

Che-Wei Tung

Chia-Heng Chen

Shu-Fang Hou

Yi-Suei Liao

Chun-Huan Chang

Yen-Wei Yeh

Chin-Hsien Chou

Chia-Ming Chang

Chun-Hsin Liu

Chin-Hao Chang

Ming-Yen Tsai

Yu-Zuo Lin

Keng-Chuan Cheng

Yan-Ting Chen

Wei-Kai Huang

A light-emitting signal generating circuit includes a first transistor, having a first terminal for receiving a first light-emitting signal, a gate terminal for receiving a first clock signal, and a second terminal that generates a control signal; a second transistor that has a first terminal for receiving a first reference voltage, a gate terminal, and a second terminal for outputting a second light-emitting signal; a first capacitor having a first terminal for receiving a second clock signal, and a second terminal coupled to the second terminal of the first transistor and a gate terminal of the second transistor, wherein a low level period of the first clock signal partially overlaps with a low level period of the second clock signal, and a falling edge of the second clock signal lags behind a falling edge of the first clock signal.

Light-emitting signal generating circuit and display device

A pixel circuit is provided. The pixel circuit includes: a light-emitting element, a driving circuit, a capacitor, a first compensation circuit, a second compensation circuit, a reset read circuit, a data writing circuit, and a light-emitting control circuit. The light-emitting element has a cathode that receives a system low voltage. The driving circuit provides a driving current based on a gate voltage. The capacitor is coupled between a gate control node and a control node. The first compensation circuit provides a system high voltage to the control node and the driving circuit. The second compensation circuit provides a reference voltage to the driving circuit. The reset read circuit provides an initial voltage to the control node and the gate control node. The data writing circuit provides a data signal to the gate control node. The light-emitting control circuit provides the driving current to the light-emitting element.

Pixel circuit

A pixel circuit is provided. A reader reads a first data voltage and a threshold voltage of a target compensation transistor on a current path of a driving current in a light-emitting driver to a control terminal of the target compensation transistor during a read period. During a light-emitting period, the reader uses a second data voltage to compensate the control terminal of the target compensation transistor, which ensures that the driving current is only related to the first data voltage. The second data voltage is twice voltage value of the first data voltage.

A display includes a first light emitting device. The first light emitting device includes a first switch and a second switch. The first switch is configured to adjust a first node according to a first clock signal. The second switch is configured to generate a first light emitting signal according to a first voltage signal. A control end of the second switch is coupled to the first node. The first clock signal switches between a first voltage level and a second voltage level. The first voltage signal has a third voltage level. The third voltage level is more than one of the first voltage level and the second voltage level and is less than the other one of the first voltage level and the second voltage level.

Display

A display apparatus is provided. The display apparatus includes a display panel and a plurality of flexible printed circuit boards. The display panel has a fan-out area and a display area. The flexible printed circuit boards are coupled to the display panel. A first side of each flexible printed circuit board is configured with a plurality of first traces for transmitting a first group of clock signals among a plurality of clock signals, and a second side of each flexible printed circuit board opposite to the first side is configured with a plurality of second traces for transmitting a second group of clock signals among the clock signals. The first group of clock signals of one of the flexible printed circuit boards and the second group of clock signals of the adjacent flexible printed circuit board are transmitted to the display area through the fan-out area together.

Display apparatus

A driving circuit includes an S stage register, a first connect line, an (S+A) stage register and a second connect line. The S stage register receives an S stage control signal through a first switch unit and a second switch unit, so that the S stage register performs voltage regulation and outputs an S stage scan signal. The first connect line is electrically connected to the first switch unit of the S stage register. A third switch unit of the (S+A) stage register is electrically connected to the first connect line and a fourth switch unit of the (S+A) stage register for receiving the S stage scan signal, so that The (S+A) stage register performs voltage regulation. The second connect line is electrically connected to the second switch unit of the S stage register and the fourth switch unit of the (S+A) stage register.

Driving circuit with multiple stage registers performing voltage regulation

A scan driver circuit including shift register units and gate control circuits is provided. The shift register units are in a peripheral area of a display panel, and for receiving first clock signals. The gate control circuits are in an active area of the display panel, and for receiving second clock signals. Each shift register unit is coupled with corresponding N of the gate control circuits, and for providing a corresponding one of the first clock signals as a control signal to the corresponding N of the gate control circuits. The corresponding N of the gate control circuits are coupled with corresponding M of gate lines. The corresponding N of the gate control circuits are for providing, according to the control signal, corresponding M of the second clock signals as M gate signals to the corresponding M of gate lines, in which M and N are positive integers.

Display panel and scan driver circuit thereof suitable for narrow border application

A display panel is provided. The display panel includes a plurality of scan lines and a gate driving circuit. The scan lines are disposed on the display panel along a first direction, and respectively provide a plurality of gate driving signals. The gate driving circuit is disposed on a first side of the display panel along a second direction. The second direction intersects the first direction. The gate driving circuit includes a plurality of bias generators and a plurality of signal output circuits. The signal output circuits are divided into a plurality of groups. The bias generators respectively correspond to the groups. The bias generators generate a plurality of first bias voltages. The groups generate the gate driving signals respectively according to the first bias voltages.

Display panel with reduced border area improving charging and discharging capacities of gate driving circuit

A driving circuit includes a S stage register, a first connect line, a (S+A) stage register and a second connect line. The S stage register receives a S stage control signal through a first switch unit and a second switch unit, so that the S stage register performs voltage regulation and outputs a S stage scan signal. The first connect line is electrically connected to the first switch unit of the S stage register. A third switch unit of the (S+A) stage register is electrically connected to the first connect line and a fourth switch unit of the (S+A) stage register for receiving the S stage scan signal, so that The (S+A) stage register performs voltage regulation. The second connect line is electrically connected to the second switch unit of the S stage register and the fourth switch unit of the (S+A) stage register.

A wire component includes a plurality of working signal lines and a plurality of transmitting lines. The working signal lines are configured to respectively provide a plurality of working signals to a driving circuit, and phases of the working signals at least partially lag each other sequentially. The transmitting lines are configured to respectively transmit the working signals, and a portion of the transmitting lines crosses the working signal lines. A first working signal line is configured to provide a first working signal; a second working signal line is configured to provide a second working signal; the first working signal immediately lags the second working signal, and the first working signal line and the second working signal line are arranged with another working signal line therebetween.

Display device and wire component

A display device is provided. The display device includes an internal driving circuit, an external circuit and a plurality of signal lines. The signal lines are electrically connected with the internal driving circuit and the external circuit. Each signal line includes N signal line sections, Ma first turning points and Mb second turning points, wherein the N signal line sections are connected with each other, each of the Ma first turning points and the Mb second turning points is located at the connecting site of the two adjacent signal line sections, N and Ma are positive integers, Mb is 0 or a positive integer, N&#x2265;3, Ma&#x2265;2, Ma+Mb&#x2264;N&#x2212;1, the resistance change rate between the two adjacent signal line sections connected with each first turning point is &#x394;R, and 0&#x3c;|&#x394;R|&#x2264;10%.

Display device

A display panel has a display region, an external circuit region located at an edge of the display panel, and a first and second wiring regions. The first wiring region is located between the second wiring region and the external circuit region. The display panel includes a pixel array, gate driving circuit groups disposed between the second wiring region and the display region, first signal line groups extended from the external circuit region to the first and second wiring region, and second signal line groups extended from the second wiring region and connected to the corresponding gate driving circuit groups. In the second wiring region, a first portion of the first signal line groups overlapped with the second signal line groups has a first width, and a second portion thereof not overlapped with the second signal line groups has a third width which is larger than the first width.

Display panel having a grading wiring design

A shift register includes a control circuit, a switching circuit, a driving circuit, and a pull-down circuit. The control circuit is configured to output a control signal having a high level during a pull-up period and a voltage-regulating period respectively. The switching circuit is configured to provide a control voltage according to the control signal and a front stage signal outputted by a front x-stage shift register during the pull-up period. The driving circuit is configured to generate a driving signal according to the control voltage provided by the switching circuit, and output a home stage scan signal based on the driving signal. The pull-down circuit is configured to pull down a voltage level of the driving signal according to a scan signal outputted by a rear y-stage shift register during a pull-down period. The switching circuit is configured to regulate the driving signal and the home stage scan signal.

Shift register and control method thereof

A shift register includes a first voltage stabilizing unit, a second voltage stabilizing unit, a main pull-down unit and a main pull-up unit. The first voltage stabilizing unit is used to pull a first driving control signal to a low voltage terminal when a first stabilizing control signal is high. The second voltage stabilizing unit is used to pull the first driving control signal to the low voltage terminal when a second stabilizing control signal is high. The main pull-down unit includes a first sub-pull-down unit controlled by a second gate-terminal signal for pulling down the first driving control signal to the low voltage terminal during a first display mode, and a second sub-pull-down unit controlled by a third gate-terminal signal for pulling down the first driving control signal to the low voltage terminal during a second display mode. The main pull-up unit is used for pulling up a first gate-terminal signal.

Shift register pulling control signals according to display mode

A shift register includes a plurality of stages of shift register circuit. Each stage of shift register circuit includes a first switch, an input circuit, a pull-down circuit, and a pull-down voltage regulator circuit. The first switch is used to output a scan signal according to a voltage level of a node and a clock signal. The input circuit is used to pull up the voltage level of the node according to a signal from a previous M-th stage of shift register circuit. The pull-down circuit is used to pull down the voltage level of the node according to the clock signal and a signal from a following L-th shift register circuit and reduce current leakage at the node. The pull-down voltage regulator circuit is used to pull down the voltage levels of the node and the scan signal according to the voltage level of the node.

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Hsin-Chu, Taiwan

Wei-Li Lin