Taiwan Semiconductor Manufacturing Comp. Ltd.

Au Optronics Corporation

Wei-Li Chen

Yeur-Luen Tu

Yu-Hung Cheng

Tung-I Lin

Cheng-Hsiang Hsieh

Chaitanya Palusa

Dirk Pfaff

Rob Abbott

Fan-ming Kuo

Chia-Shiung Tsai

Cheng-Ta Wu

Ru-Liang Lee

Po-Hsiang Lan

Shi-Hung Wang

Chewn-Pu Jou

Ching-Wei Tsai

Yun-Han Lee

Kuang-Kai Yen

Rolando Ramirez

Alexander Kalnitsky

Fu-Lung Hsueh

Yi-Lin Chuang

Cheng-Lung Wu

Shih-Pei Chou

Yung-Chin Hou

Ching-Fang Chen

Wei-Pin Changchien

Yung-Hsu Chuang

Tsung-Hsiung Lee

Shih-Hung Lan

Lee-Chung Lu

Huan-Neng Chen

Jhy-Jyi Sze

Shyh-Fann Ting

Hsieh-Hung Hsieh

Chin-Szu Lee

Cheng-Yi Wu

Jian-Shin Tsai

Chao-Ching Chang

Yi-Hsuan Liu

Min-Hui Lin

Kuo-Hsien Cheng

Mao-Ruei Li

Tsung-Hsiung Li

Fan-Ming Kuo

Tan-Li Chou

Te-Hai Tseng

Chung-Yu Hsieh

Tung-Hsiung Tseng

Kheng-Guan Tan

The present disclosure provides a semiconductor structure, including: a semiconductor device layer including a first surface and a second surface, wherein the first surface is at a front side of the semiconductor device layer, and the second surface is at a backside of the semiconductor device layer; an insulating layer above the second surface of the semiconductor device; and a through-silicon via (TSV) traversing the insulating layer. Associated manufacturing methods of the same are also provided.

Semiconductor structure having a silicon active layer formed over a SiGe etch stop layer and an insulating layer with a through silicon via (TSV) passed therethrough

A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.

Multi-tap decision feed-forward equalizer with precursor and postcursor taps

An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.

SerDes receiver with optimized CDR pulse shaping

A data verifying method, a chip, and a verifying apparatus are provided. In the method, an encoder is provided for at least one processing circuit of a chip. One or more transmitting data of a to-be-test circuit of the processing circuit is encoded through the encoder to generate one or more parity data. The transmitting data is a computing result generated by the to-be-test circuit. The parity data is transmitted without the transmitting data. The parity data is used for data verification of the transmitting data.

Data verifying method, chip, and verifying apparatus

Method for manufacturing a semiconductor structure comprising a semiconductor device layer formed on a tem, porary substrate having a graded SiGe etch stop layer therebetween

Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of one or more electronic architectural designs for an electronic device. The EDA of the present disclosure identifies one or more electronic architectural features from the one or more electronic architectural designs. In some situations, the EDA of the present disclosure can manipulate one or more electronic architectural models over multiple iterations using a machine learning process until one or more electronic architectural models from among the one or more electronic architectural models satisfy one or more electronic design targets. The EDA of the present disclosure substitutes the one or more electronic architectural models that satisfy the one or more electronic design targets for the one or more electronic architectural features in the one or more electronic architectural designs to optimize the one or more electronic architectural designs. The EDA of the present disclosure can substitute the one or more electronic architectural models before, during, and/or after designing, simulating, analyzing, and/or verifying of the one or more electronic architectural designs to effectively decrease the time to market (TTM) for the electronic device.

Machine-learning design enablement platform

A method for fabricating a semiconductor device includes providing a first wafer comprising a substrate and a first semiconductor material layer, bonding the first wafer to a second wafer, the second wafer comprising a sacrificial layer and a second semiconductor material layer, removing the sacrificial layer, patterning the bonded wafers to create a first structure and a second structure, removing the second semiconductor material from the first structure, forming a first type of transistor in the first semiconductor material of the first structure, and forming a second type of transistor in the second semiconductor material of the second structure.

Method of forming source/drain regions of transistors

Serdes receiver with optimized CDR pulse shaping

Transistor channel

Backside illuminated (BSI) image sensor devices are described as having pixel isolation structures formed on a sacrificial substrate. A photolayer is epitaxially grown over the pixel isolation structures. Radiation-detecting regions are formed in the photolayer adjacent to the pixel isolation structures. The pixel isolation structures include a dielectric material. The radiation-detecting regions include photodiodes. A backside surface of the BSI image sensor device is produced by planarized removal of the sacrificial substrate to physically expose the pixel isolation structures or at least optically expose the photolayer.

Pixel isolation device and fabrication method

Growing community of inventors

Tainan, Taiwan

Wei-Li Chen