Hrl Laboratories, LLC

Wei L Yi

Jack A Crowell

Elias A Flores

Praveen K Pilly

Charles E Martin

Jose Cruz-Albrecht

Soheil Kolouri

Xiwei Bai

Thomas C Oh

Philip A King

Kenneth K Tsang

Stephen K Lam

A neuron circuit, comprising first and second NDR devices biased each with opposite polarities, said first and second NDR devices being coupled to first and second grounded capacitors.

Scalable excitatory and inhibitory neuron circuitry based on vanadium dioxide relaxation oscillators

A circuit for performing energy-efficient and high-throughput multiply-accumulate (MAC) arithmetic dot-product operations and convolution computations includes a two dimensional crossbar array comprising a plurality of row inputs and at least one column having a plurality of column circuits, wherein each column circuit is coupled to a respective row input. Each respective column circuit includes an excitatory memristor neuron circuit having an input coupled to a respective row input, a first synapse circuit coupled to an output of the excitatory memristor neuron circuit, the first synapse circuit having a first output, an inhibitory memristor neuron circuit having an input coupled to the respective row input, and a second synapse circuit coupled to an output of the inhibitory memristor neuron circuit, the second synapse circuit having a second output. An output memristor neuron circuit is coupled to the first output and second output of each column circuit and has an output.

Bipolar all-memristor circuit for in-memory computing

A memory circuit configured to perform multiply-accumulate (MAC) operations for performance of an artificial neural network includes a series of synapse cells arranged in a cross-bar array. Each cell includes a memory transistor connected in series with a memristor. The memory circuit also includes input lines connected to the source terminal of the memory transistor in each cell, output lines connected to an output terminal of the memristor in each cell, and programming lines coupled to a gate terminal of the memory transistor in each cell. The memristor of each cell is configured to store a conductance value representative of a synaptic weight of a synapse connected to a neuron in the artificial neural network, and the memory transistor of each cell is configured to store a threshold voltage representative of a synaptic importance value of the synapse connected to the neuron in the artificial neural network.

Neuromorphic memory circuit and method of neurogenesis for an artificial neural network

An integrated neuron circuit structure comprising at least one thin-film resistor, one Metal Insulator Metal capacitor and one Negative Differential Resistance device.

Scalable, stackable, and BEOL-process compatible integrated neuron circuit

A vanadium dioxide (VO)-based threshold switch device exhibiting current-controlled negative differential resistance (S-type NDR), an electrical oscillator circuit based on the threshold switch device, a wafer including a plurality of said devices, and a method of manufacturing said device are provided. The VO-based threshold switch device exhibits volatile resistance switching and current-controlled negative differential resistance from the first time a sweeping voltage or voltage pulse is applied across the device without being treated with an electroforming process. Furthermore, the device exhibits substantially identical switching characteristics over at least 10switching operations between a high resistance state (HRS) and a low resistance state (LRS), and a plurality of threshold switch devices exhibits a threshold voltage Vspreading of less than about 25%. The threshold switch device may be included in an oscillator circuit to produce an astable oscillator that may serve as a functional building block in spiking-neuron based neuromorphic computing.

Scalable and low-voltage electroforming-free nanoscale vanadium dioxide threshold switch devices and relaxation oscillators with current controlled negative differential resistance

An electronic device comprising a substrate having a surface; a first electrode wire extending on said surface along a first direction; a vanadium pentoxide layer extending on and contacting at least a portion of said first electrode; a second electrode wire extending over said surface along a second direction, such that the second electrode wire extends on and contacts at least a portion of the vanadium pentoxide layer above the first electrode wire at a crossing point; wherein a region of vanadium dioxide is included in said vanadium pentoxide layer between the first and second electrodes at said crossing point.

Growing community of inventors

Moorpark, CA, United States of America

Wei L Yi