Industrial Technology Research Institute

Wei-Kuo Chia

Chun-Kai Huang

Ruen-rone Lee

Yu-Ming Lin

Chun-Yang Cheng

Yea-Yun Yang

Chun-Chieh Hsiao

Jiun-Ming Chu

Shu-Fang Hwang

Jan-Han Hsiao

Erh-Chiao Wang

Bao-Tyan Wang

Jin-Han Hsiao

A method for drawing a 3D triangle includes decomposing polygons into triangles. The triangles are then truncated into trapezoids, so that they may be drawn in the same direction, such as always top to bottom and left to right. The Z error values are determined for each trapezoid. This allows initial Z values to be correct. The ERROR values may be determined for other triangle attributes such as color, translucence, and texture.

Method for rendering 3D triangle primitives

A linear address organization for physically storing mip maps and rip maps in memory is disclosed. The subsampled data arrays of the mip maps and rip maps are sequentially stored in continuous subsequences of a continuous sequence of memory addresses. The subsequences of addresses are assigned in order of level of subsampling of the data arrays which make up the mip map or rip map. In the case of a mip map, the subsequences are assigned to the data arrays in order of increasing level of subsampling. In the case of rip maps, the data arrays are segregated into groups according to a first one of the two subsampling directions, such that each array in a particular group has the same level of subsampling in the first direction. Subsequences are assigned to each group of data arrays. The addresses of the subsequences are assigned within each group on a span by span basis where a span includes the texture data in a particular direction of each data array in order of increasing level in the second one of the two subsampling directions. Address generators are also disclosed for assisting in generating linear addresses to texture data with specific coordinates (u,v) in arrays having particular levels of subsampling.

Mip map/rip map texture linear addressing memory organization and

An improved computer graphics memory architecture has a frame buffer and a Z buffer, each having a forward and reverse part, each of which is wide enough to handle two pixels of data. A data path is connected to the buffers so that in a 3-D application, a full pixel of both color and Z-value data is transported along the data path in a single I/O transaction. In a 2-D application, two pixels of data are transported along the data path in a single I/O transaction. In a preferred embodiment, both the frame and Z buffers are divided into two parts each wide enough to handle one pixel of data part. In 3-D applications, a data path is selectively connected to the buffers in a manner so that one pixel of color data and one pixel of Z-value data are simultaneously transported to the drawing processor during each I/O transaction. In this preferred embodiment, a first reversing switch such as a multiplexer circuit, is provided to reverse data that arrives from the buffer in reverse order. A second reversing switch, such as a multiplexer circuit, is provided to return the data to the proper buffer after processing. In a preferred embodiment for 2-D applications, two pixels of data are transported to the drawing processor each I/O transaction. In this preferred embodiment, a third reversing switch is provided to reverse data that arrives from the buffer in reverse order. A fourth reversing switch is provided to return the data to the proper buffer after processing.

Computer graphics memory architecture which processes a full pixel of 3D

An apparatus and method for blending pixels of a source object and a destination plane of view of 3-D space. The source object overlaps the destination plane of view. Furthermore, the 3-D space may contain an atmospheric light diffusion, i.e., fog or smoke, which produces a 'fog effect.' The apparatus includes multiplexer circuitry which receives first, second, third, fourth and fifth control signals. The multiplexer circuitry also receives a fog blend factor, a source alpha, a destination alpha, a source color, a destination color, a fog color and one. In response to the control signals, the multiplexer circuitry selects three outputs. In particular, in response to the first, second and third control signals, the multiplexer selects as the first output, either: the destination alpha, the source alpha, the fog blend factor, one, the destination color, or one minus one of the aforementioned choices. In response to the first, fourth and fifth control signals, the multiplexer circuitry selects as the second output either: the destination alpha, the source alpha, the fog blend factor, one, the source color, or one minus one of the aforementioned choices. In response to the first control signal, the multiplexer circuitry selects as the third output the destination color or the fog color. The apparatus also includes calculation circuitry which produces a first product, of the source color and the first output of the multiplexer circuitry, produces a second product of the second and third outputs of the multiplexer circuitry, and thereafter adds the two products together.

Apparatus for blending pixels of a source object and destination plane

An address generator is disclosed for performing 2-D virtual coordinate to linear physical memory address conversion. The address generator has an edge walking circuit which receives a 2-D virtual coordinate of a first pixel on a first edge of an object displayed on the display screen. The edge walking circuit selectively outputs a 2-D virtual coordinate of a second pixel which intercepts the first edge of the object at an adjacent pixel row or column to the first pixel. The address generator also has a span expansion circuit which receives the 2-D virtual coordinate of the second pixel. The span expansion circuit selectively expands the 2-D virtual coordinate of the second pixel, according to the number of bits used to represent each pixel and the amount of information which can be accessed at a time from memory. This produces first and second expanded coordinates of the second pixel. Furthermore, the address generator has a linear address circuit which receives the first and second expanded coordinates of the second pixel. The linear address circuit outputs a linear physical address of the second pixel in memory.

Virtual coordinate to linear physical memory address converter for

A process and apparatus are disclosed for obtaining a texture color value C.sub.r for an object surface point from two texture color values C.sub.ri and C.sub.rj (which themselves may be interpolated texture color values), of texture data points C.sub.i and C.sub.j, respectively. The object surface point is a distance W from the texture data point C.sub.i and a distance 1-W from the object surface point C.sub.j, where W is an n-bit value. The process includes the steps of multiplying each of the texture colors C.sub.ri and C.sub.rj by each integer from 0 to 2.sup.n-1 to produce 2.sup.n -1 products for each color. The product of C.sub.ri with 2.sup.n-1 -W' and the product of C.sub.rj with W' are selected from these produced products, where W' is the rounded product of W and 2.sup.n-1. The two selected products are added together to produce the sum (2.sup.n-1 -W').multidot.C.sub.ri +W'.multidot.C.sub.rj, and the sum thus produced is divided by 2.sup.n-1 to produce the interpolated color. The apparatus for producing the interpolated color uses integer arithmetic for producing the texture color and can operate in a pipelined fashion.

Texture filter apparatus for computer graphics system

A pixel block transfer system has a shifter, at least two registers, an extractor and a mask. Parameter evaluation logic is used to generate most of the parameters needed in the pixel block transfer. The start address of the source block, the start address of the destination block, the number of pixels in the source block and the number of rows in the source block are input to the parameter evaluation logic. The parameter evaluation logic then determines the left shift number, the number of read data, the number of write data, the two write flag, the two read flag, the left mask number and the right mask number. The start addresses, the flags and the read and write numbers are sent to a state machine. These are used to control the pixel block transfer. The left shift number is sent to the shifter and the extractor. It signifies the number of pixels to be shifted left. The left and right mask numbers are sent to the mask to control which pixels are masked and, therefore, not modifiable. The state machine also sends left and right enable signals to the mask.

Growing community of inventors

HsinChu, Taiwan

Wei-Kuo Chia