Taiwan Semiconductor Manufacturing Comp. Ltd.

Wei-Kun Yeh

Chi-Hsiang Lee

Hua-Yu Yang

An-Min Chiang

Chiarn-Lung Lee

An-Ming Chiang

Hua Yu Yang

An Min Chiang

Jun-Kai Peng

An Ming Chiang

A process for reducing the dark current generation of an image sensor cell, fabricated on a semiconductor substrate, has been developed. The process features the use of polysilicon pad structure, formed simultaneously with a polysilicon gate structure of a reset transistor, with the polysilicon pad structure located overlying, and contacting, a portion of the top surface of the photodiode element, of the image sensor cell. A small diameter opening, in a composite polysilicon-silicon oxide layer, exposes the portion of photodiode element to be contacted by the polysilicon pad structure. The small diameter opening is created using a procedure which allows the surface of the photodiode element, exposed in the small diameter opening to experience only a minimum of RIE processing at end point, thus minimizing damage to the surface of the photodiode element, and thus reducing dark current generation. A metal contact structure, used to communicate with the photodiode element, is then formed on the polysilicon pad structure.

Method of reducing dark current for an image sensor device via use of a polysilicon pad

An active pixel sensor cell, and the process for forming the active pixel sensor cell, featuring a pinned photodiode structure, and a readout region, located in a region of the pinned photodiode structure, has been developed. The process features the formation of a N&plus; readout region, performed simultaneously with the formation of the N&plus; source/drain region of the reset transistor, however with the N&plus; readout region placed in an area to be used for the pinned photodiode structure. The pinned photodiode structure is next formed via formation of a lightly doped N type well region, used as the lower segment of the pinned photodiode structure, followed by the formation of P&plus; region, used as the top segment of the pinned photodiode structure, with the N&plus; readout region, surrounded by the P&plus; region. The placement of the N&plus; readout region, in a region of the pinned photodiode structure, eliminates the need for a transfer transistor, for the active pixel sensor cell, and results in a higher signal to noise ratio, as well as lower dark current generation, than counterparts fabricated without the use of the process, and structure, of this invention.

Pinned photodiode structure in a 3T active pixel sensor

A method of forming an image sensor is disclosed. A partially processed semiconductor wafer is provide, containing p-type and/or n-type regions which are bounded by isolation regions and with gate oxide layers grown on the surfaces upon which gate electrode structures are disposed, some of said gate electrode structures will serve as gate electrodes of image sensor transistors. Ions are implanted to form source/drain structures about the said gate electrode structures. To form photodiodes ions are implanted in two steps overlapping a source/drain region. A deeper implant provides a low charge carrier density region and a shallow implant provides a high charge carrier density region near the surface. A blanket transparent insulating layer is deposited.

CMOS image sensor n-type pin-diode structure

In an improved method for etching a groove n the uppermost layer of a semiconductor wafer, a conventional anisotropic etch is performed to achieve a narrow groove and an isotropic etch is performed to widen the groove at the device surface and thereby round the edges where the walls of the groove meet the surface of the wafer. During a later step of applying a protective tape to the device side of the wafer to protect it during a step of grinding the back of the wafer, the rounded edges of the groove are unlikely to cut through the adhesive layer of the tape and thereby cause particles of adhesive to remain on the wafer surface when the tape is removes.

Method for etching passivation layer of wafer

A method of forming an image sensor is disclosed. A partially processed semiconductor wafer is provide, containing p-type and/or n-type regions which are bounded by isolation regions and with gate oxide layers grown on the surfaces upon which gate electrode structures are disposed, some of said gate electrode structures will serve as gate electrodes of image sensor transistors. Ions are implanted to form source/drain structures about the said gate electrode structures, with an extended region for source drains bordering photodiode regions. Ions are implanted to form photodiodes, overlapping the extended bordering source drain regions. A blanket transparent insulating layer is deposited.

Method of manufacturing for CMOS image sensor

A process of fabricating an image sensor cell, on a semiconductor substrate, with the image sensor cell exhibiting low dark current generation, and high signal to noise ratio, has been developed. The process features the use of a photoresist shape, used to protect a previously formed photodiode element, from an reactive ion etching procedure, used to define insulator spacers on the sides of a polysilicon gate structure, of a reset transistor structure This process sequence avoids damage to the surface of an N type component, of the photodiode element, resulting in the improved electrical characteristics, when compared to counterpart image sensor cells, in which the photodiode element was subjected to the insulator spacer definition procedure.

Growing community of inventors

Hsin-Chu, Taiwan

Wei-Kun Yeh