Intel Corporation

Wei Keat Loh

Saikumar Jayaraman

Daewoong Suh

Mitesh C Patel

Edward L Martin

Tiffany Byrne

Sheau Hooi Lim

Stephen E Lehman

Yoong Tatt P Chin

Mohd Erwan B Basiron

Yew Wee Cheong

Kang Eu Ong

Shaw Fong Wong

Al Ling Low

Au Seong Wong

Yee Hao Ho

Disclosed are embodiments of a lower integrated circuit (IC) package structure for a package-on-package (PoP) assembly. The lower IC package structure includes an interposer having pads to mate with terminals of an upper IC package. An encapsulant material is disposed in the lower IC package, and this encapsulant may be disposed proximate one or more IC die. An upper IC package may be coupled with the lower IC package to form a PoP assembly. Such a PoP assembly may be disposed on a mainboard or other circuit board, and may form part of a computing system. Other embodiments are described and claimed.

Lower IC package structure for coupling with an upper IC package to form a package-on-package (PoP) assembly and PoP assembly including such a lower IC package structure

A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.

Stress-relief layers and stress-compensation collars with low-temperature solders for board-level joints, and processes of making same

An apparatus having and method of forming grooves in the surface of a substrate adjacent and parallel to sidewall locations for circuit chips or die mounted on the surface. The grooves have physical dimensions to retain fill material formed between the packages and the surface of the substrate so that the fill material does not bridge between chips, thus reducing warping of the substrate due to mismatches in coefficient of thermal expansion (CTE) between the fill material, the substrate, the chips, and mold material formed over the substrate, under fill, and chips.

Substrate grooves to reduce underfill fillet bridging

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Penang, Malaysia

Wei Keat Loh