Cadence Design Systems, Inc.

Silicon Perspective Corporation

Quickturn Design Systems, Inc.

Wei-Jin Dai

Hsi-Chuan Chen

Mitsuru Igusa

Chin-Chi Teng

Wei-Lun Kao

Shiu-Ping Chao

Kit-Lam Cheong

Stephen Paul Sample

Ping-Chih Wu

Patrick John Eichenseer

Dennis Huang

Jui-Ming Chang

Dam Van Bui

Lung-Chun Liu

Thad Clay McCracken

Daw Yang Shyong

Louis Galbiati, Iii

Joseph Varghese

Junjing Yan

Jia-Jye Shen

Ping Chao

Disclosed are improved approaches for implementing design entry. An efficient, spread-sheet based representation is provided for both the instances and connections in a design. Visualization techniques provide the user with visual cues, to direct and identify compatible connection points, unconnected instances, and contention situations. Techniques are disclosed to automatically filter the spreadsheet in a variety of ways, to help the user to dynamically hide portions of the design space that are not interesting at a particular time, and thus to improve the efficiency with which they can work.

Method and system for implementing electronic design entry

A clock tree syntheses (CTS) tool designs a group of clock trees to be incorporated into an IC design for conveying separate clock signals to clock sinks within the IC with a predetermined maximum group skew. The tool initially generates a separate, independently balanced, first clock tree design for each clock tree and then processes each first clock tree design to estimate an average path delay of the clock signal it conveys to each sink. The CTS tool then selects, as a target path delay, a highest average delay from among average delays computed for all clock trees. Thereafter the CTS tool generates a separate second clock tree design for each clock tree that is balanced to limit a difference between the target path delay and an estimated delay to each sink to a value that ensures a group clock skew will reside within the predetermined maximum group skew.

Clock tree synthesis for mixed domain clocks

An integrated circuit (IC) layout process is organized into two phases. During the Phase of the process, a preliminary placement plan is generated fixing the position of every cell of an IC design described by a gate level netlist. A trial routing plan is also generated establishing approximate routes of the nets that are to interconnect cell terminals. The placement plan and the trial routing plan are then iteratively analyzed and modified as necessary to ensure that the layout meets various signal path timing, signal integrity, and power distribution and other constraints. Thereafter, at the start of Phase of the layout process, the trial routing plan is converted into a detailed routing plan specifying in detail the exact routes to be followed by all nets. The placement plan and detailed routing plan are then iteratively analyzed and modified as necessary to ensure that they meet all design constraints.

IC layout system having separate trial and detailed routing phases

A method is disclosed for synthesizing a clock tree for a partitioned integrated circuit (IC) layout comprising a plurality of base level partitions and a top level partition each occupying a separate area of a semiconductor substrate. The base level partitions include syncs to be clocked by edges of a clock signal applied to an entry node within the area occupied by the top level partition. In accordance with the method, a plurality of independently balanced subtrees are separately synthesized. Each subtree resides within the area occupied by a separate base level partition and includes a start point at a perimeter of the area occupied by that base level partition and a network of buffers and signal paths for conveying a clock signal edge from the start point to each sync included within that area. Thereafter a top level portion of the clock tree is synthesized. The top level portion of the subtree resides within the substrate area containing the top level partition and conveys the clock signal from the entry point to the start point of each synthesized subtree.

Clock tree synthesis for a hierarchically partitioned IC layout

An integrated circuit (IC) layout system initially modifies a netlist describing an IC as a hierarchy of circuit modules to combine clusters of cells forming selected modules so that they form a smaller number of larger cells. This reduces the number of cells forming the IC, thereby reducing the time the system needs to generate an IC layout. The system then generates a trial layout of the IC described by the modified netlist. Based on the shape and position of the area each module occupies in the trial layout, the system estimates the shape and position of a substrate area each module would require in a layout where module areas did not overlap. The system then divides the IC design into several partitions, each including separate set of the modules forming the IC, and creates a partition plan allocating substrate space to each partition based on the estimated space requirement of each module assigned to that partition. The system also creates a timing budget allocating signal path timing constraints among the partitions based on an timing analysis of signal paths delays in the trial layout. Thereafter the system independently lays out each IC partition so that it satisfies that partition's spatial and timing constraints as indicated by the partition plan and timing budget. The partition layouts are then assembled to form a complete IC layout.

Scalable, partitioning integrated circuit layout system

When generating a layout for an integrated; circuit (IC) based on a netlist design, a trial layout which need only satisfy the various spatial, power and other constraints, but need not satisfy the layout's timing constraints, is quickly produced. The trial layout acts as a basis for estimating sizes and positions of substrate areas needed to accommodate various modules of the IC and for estimating delays through various signal paths having timing constraints. After producing the trial layout, the IC design is divided into several partitions with modules being grouped into partitions in accordance with their proximity to one another in the trial layout. A floor plan is created which imposes spatial constraints on each partition based on the estimated size and position within the trial layout of the modules forming the partition. A timing budget is also created which allocates portions of each timing constraint to the partitions based on the time delay estimates derived from the trial layout. The partitions are then separately placed and routed a manner consistent with the spatial and timing constraints imposed on each partition by the floor plan and the timing budget.

Method for generating a partitioned IC layout

Disclosed herein is a method for dividing an integrated circuit (IC) design into several circuit partitions, each including one or more circuit modules, and then separately carrying out placement and routing for each circuit partition, with each partition being implemented within a separate area of an IC substrate. The method initially generates a whole-chip trial placement that tends to cluster cells of each circuit module together. An IC substrate floor plan assigning modules to various partitions is prepared, with the size, shape and relative position of each partition being determined by size, shape and relative position of areas of the substrate occupied by those modules in the trial floor plan. A trial routing is also performed with information on which to base a pin assignment plan for each module. A detailed placement and routing process is then independently performed for each partition, with placement and routing of cells within each partition constrained by the floor plan and pin assignment plan.

Integrated circuit partitioning placement and routing system

In computer-aided electronic design automation software, a placement system biases clustering of cells according to their hierarchical design while optimizing placement for controlling die size and total wire length. The placement system also provides for slack distribution, row improvement and randomization during partitioning. Floor plans based on trial placement and placement guiding blocks are also described.

Design hierarchy-based placement

A method for optimizing a logical design for emulation. The present invention optimzes latch-based designs by transforming them into a flip-flop based circuit. The design is analyzed to determine whether any consecutive latches are clocked by the same clock signal. If consecutive latches are clocked by the same clock signal, for example, the same phase of the same master clock, a transparency condition exists. Transparent latches are transformed into either a flip-flop/buffer/multiplexer circuit or a buffer circuit depending upon whether the latch in the logic design has an enable input. If consecutive latches in a design are clocked by different clock signals, i.e., different phases of the master clock, no transparency condition exists. Non-transparent latches are transformed into a flip-flop.

Latch optimization in hardware logic emulation systems

An emulation system and method that reduces or eliminates the number of timing errors such as hold time violations when implementing a netlist description of an integrated circuit. The emulation system comprises a plurality of reprogrammable logic circuits and a plurality of reprogrammable interconnect circuits. The netlist description is optimized to reduce the number of timing violations by removing the occurences of gated clocks from the netlist, partitioning the netlist description by taking into account the occurence of timing violations and ensuring that retain state nets are implemented properly.

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Cupertino, CA, United States of America

Wei-Jin Dai