Taiwan Semiconductor Manufacturing Comp. Ltd.

Wei-Jhih Wang

Cheng-Cheng Kuo

Yuan-Yao Chang

Chia-Wei Huang

Chia-Chia Kan

Yuan-yao Chang

Chia Wei Huang

The present disclosure provides a wafer. The wafer includes a die, a scribe line adjacent to the die, and a test circuit adjacent to the scribe line. The test circuit includes a first switch, a second switch, and a third switch. The first switch has a first node coupled to a first device-under-test and a second node coupled to a first signal supply node. The second switch has a first node coupled to the second DUT and a second node coupled to the first signal supply node. The third switch has a first node directly coupled to the first DUT and the second DUT. The third switch has a second node coupled to a second signal supply node. The third switch selectively couples both of the first DUT and the second DUT to the second signal supply node.

Test circuit and method for operating the same

The present disclosure provides a method of analyzing a semiconductor device. The method includes providing a first transistor, a second transistor disposed adjacent to the first transistor, and a gate electrode common to the first transistor and the second transistor; connecting a power-supply voltage (V) to the gate electrode to turn on the first transistor, determining a first threshold voltage (V) based on the power-supply voltage; switching the power-supply voltage to a ground voltage (V); connecting the ground voltage to the gate electrode to turn on the second transistor; and determining a second threshold voltage based on the ground voltage.

Semiconductor device and analyzing method thereof

Growing community of inventors

Hsinchu, Taiwan

Wei-Jhih Wang