International Business Machines Corporation

National Yang Ming Chiao Tung University

Faraday Technology Corporation

Wei Hwang

Sang Hoo Dhong

Hao-I Yang

Nicky C Lu

Ching-Te Chuang

Po-Tsang Huang

Rajiv V Joshi

Ming-Hung Chang

Walter H Henkels

Ming-Hsien Tu

Gary Bela Bronner

Hyun J Shin

Shyh-Jye Jou

Wei-Chiang Shih

Louis L Hsu

Toshiaki Kirihata

Stephen McConnell Gates

Chia-Cheng Chen

Li-Kong Wang

Lewis M Terman

Wei-Chih Hsieh

Walter Harvey Henkels, Deceased

Philip George Emma

Stephen Victor Kosonocky

Yasunao Katayama

Matthew R Wordeman

Wing Kin Luk

Terry I Chappell

Chun-Yi Wu

Nan-Chun Lien

Dao-Ping Wang

Albert Thomas Williams

David F Heidel

Yi-Te Chiu

Yi-Wei Lin

Christophe Robert Tretz

George Diedrich Gristede

Chien-Yu Lu

Mao-Chih Hsia

Chung-Ying Hsieh

Shu-Wei Chang

Wen-Yen Liu

Chung-Hsien Hua

Terence B Hook

Yoichi Taira

Stanley Everett Schuster

Jian J Xu

Prabhakar Nandavar Kudva

Robert Louis Franch

Bijan Davari

Frank F Fang

Chang Chyi Tsuei

John E Andersen

Ming-Chien Tsai

Bertrand M Grossman

Tien-Hung Lin

Shu-Lin Lai

Kun-Ti Lee

Xiaodong Xiao

Jihi-Yu Lin

Hung-Yu Li

Wei-Nan Liao

Kun Wu

Chi-Shin Chang

Kuen-Di Lee

Shi-Wen Chen

Yung-Wei Lin

San H Dhong

Henkles, Walter H

Fang-Shi Jordan Lai

Daeje Chin

Wei-Chih Hseih

Mu-Tien Chang

Chi-Chen Lai

Chi-Wei Peng

Christopher M Chu

Shyh-Chyi Yang

Jian-Hua Wu

Yeh-Lin Chu

Thomas Doderer

Chi-Hsin Chang

Hung-Pin Lu

Philip George Emmma

Chien-Hen Chen

A neural-signal amplifier includes an amplifier, a switched-capacitor circuit-input unit, a switched-capacitor feedback-circuit unit, and a switched-capacitor circuit-output unit. Each of the switched-capacitor circuit-input unit, the switched-capacitor feedback-circuit unit, and the switched-capacitor circuit-output unit includes a plurality of differential switches, a plurality of common mode switches, and a plurality of capacitors. By controlling the switches to turn on or performing the switched-capacitor operation, the neural-signal amplifier is controlled to suppress the DC drift and reconstruct the DC input of the common-mode power supply.

Neural-signal amplifier and multi-channel neural-signal amplifying system

A multi-port SRAM with shared write bit-line architecture and selective read path for low power operation includes a first memory cell, a second memory cell, and a common switch set. The second memory cell makes use of the common switch set to share the A-port write bit-line and the B-port write bit-line with the first memory cell so as to reduce half write bit-line number and reduce the write current consumption caused by pre-charging the bit-line to VDD. It also provides a selective read path structure for read operation. Replacing the ground connection in the read port with a virtual VSS controlled by a Y-select signal reduces read-port current consumption.

Multi-port SRAM with shared write bit-line architecture and selective read path for low power operation

A 10-transistor dual-port SRAM with shared bit-line architecture includes a first memory cell and a second memory cell. The first memory cell has a first storage unit, a first switch set, and a second switch set. The second memory cell has a second storage unit, a third switch set, and a fourth switch set. The second switch set is coupled to a complement first A-port bit line and a complement first B-port bit line, and connected to the first storage unit. The third switch set is connected to a complement second A-port bit line, a complement second B-port bit line, and the second storage unit. Thus, the second memory cell can make use of the third switch set to share the complement first A-port bit line and the complement first B-port bit line with the first memory cell.

Ten-transistor dual-port SRAM with shared bit-line architecture

A static random access memory apparatus and a bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.

Static random access memory apparatus and bit-line voltage controller thereof

The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately.

Oscillato based on a 6T SRAM for measuring the bias temperature instability

A static random access memory includes a pre-charger, a first cell column array/peripheral circuit, and a first ripple buffer. The pre-charger is connected to a first local bit line in order to pre-charge the first local bit line. The first cell column array/peripheral circuit is connected to the first local bit line and has a plurality of cells for temporarily storing data. The cells are connected to the first local bit line. The first ripple buffer is connected to the first local bit line and a second local bit line in order to send the data from the first local bit line to the second local bit line.

Static random access memory with ripple bit lines/search lines for improving current leakage/variation tolerance and density/performance

A SRAM that keeps the memory cell array under a low voltage in the Standby mode and Write mode, and raises the memory cell array supply voltage to a high voltage in the Read mode. A SRAM comprising: at least one memory cell circuit, comprising a latch circuit with at least two inverters, and comprising two power receiving terminals for receiving power; and a power supplying circuit, for providing the power to the memory cell circuit, such that the voltages at the power receiving terminals of the latch circuit is below a predetermined voltage level when data is written to the latch circuit. In one embodiment, the memory cell circuit includes a plurality of data accessing terminals and the data accessing terminals are respectively controlled by at least two pass-transistor switch devices.

Low power static random access memory

An innovative dual-port subthreshold static random access memory (SRAM) cell for sub-threshold voltage operation is disclosed. During write mode, the dual-port subthreshold SRAM cell would cut off the positive feedback loop of the inverters and utilize the reverse short-channel effect to enhance write capability. The single-ended read/write port structure further reduces power consumption of the lengthy bit line. Therefore, the dual-port subthreshold SRAM cell is a suitable for long operation in a first-in first-out memory system. Although the lower voltage reduces the stability of the memory cell, the dual-port subthreshold SRAM cell of the present invention can still stably operate.

Dual-port subthreshold SRAM cell

A method buffers clock skew by using a logical effort, and is applicable to a clock tree that stays in a strong-inversion region, a moderate-inversion region, or a weak-inversion region. The method includes establishing in the clock tree a temperature sensor and a tunable-width buffer, and establishing width and temperature comparative lists according to a logical effort equation, for the tunable-width buffer to be individually applied to the strong-inversion region, the moderate-inversion region, and the weak-inversion region; selecting one from the width and temperature comparative lists that corresponds to one of the inversion regions in which the clock tree stays, enabling the temperature sensor to sense a temperature, and searching the selected width and temperature comparative list for a width that corresponds to the temperature sensed by the temperature sensor; and enabling the tunable-width buffer to perform a width modulation process according to the searched width.

Method for buffering clock skew by using a logical effort

A static random access memory cell includes a latch unit. The latch unit includes a bi-inverting circuit and a switching circuit. The bi-inverting circuit has a first terminal and a second terminal. The switching circuit is electrically connected between the first terminal and the second terminal, wherein when the switching circuit is turned on, the switching circuit forms a feedback between the first terminal and the second terminal for latching the latch unit; and when the switching circuit is turned off, the feedback is removed to cause the SRAM cell to write a data bit to the latch unit.

Static random access memory cell and method of operating the same

On-chip active decoupling capacitors for regulating the voltage of an integrated circuit include a reference voltage generator, a latch-based comparator and switched DECAPs. The latched-based comparator is for comparing a reference voltage generated by the reference voltage generator and a supply voltage of the integrated circuit and outputting a comparison result. The switched DECAPs includes at least two capacitors and a plurality of switches, and coupling the at least two capacitors into a parallel configuration to sink current or a series configuration to source current based on the comparison result output by the latch-based comparator. The aforementioned on-chip active decoupling capacitors not only have lower power consumption, but also larger detection range.

On-chip active decoupling capacitors for regulating voltage of an integrated circuit

A fully on-chip temperature, process, and voltage sensor includes a voltage sensor, a process sensor and a temperature sensor. The temperature sensor includes a bias current generator, a ring oscillator, a fixed pulse generator, an AND gate, and a first counter. The bias current generator generates an output current related to temperature according to the operating voltage of chip. The ring oscillator generates an oscillation signal according to the output current. The fixed pulse generator generates a fixed pulse signal. The AND gate is connected to the ring oscillator and the fixed pulse generator for performing a logic AND operation on the oscillation signal and the fixed pulse signal, and generating a temperature sensor signal.

Fully-on-chip temperature, process, and voltage sensor system

The present invention proposes a gate oxide breakdown-withstanding power switch structure, which is connected with an SRAM and comprises a first CMOS switch and a second CMOS switch respectively having different gate-oxide thicknesses or different threshold voltages. The CMOS switch, which has a normal gate-oxide thickness or a normal threshold voltage, provides current for the SRAM to wake up the SRAM from a standby or sleep mode to an active mode. The CMOS switch, which has a thicker gate-oxide thickness or a higher threshold voltage, provides current for the SRAM to work in an active mode. The present invention prevents a power switch from gate-oxide breakdown lest noise margin, stabilization and performance of SRAM be affected.

Gate oxide breakdown-withstanding power switch structure

A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation.

Data-aware dynamic supply random access memory

A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.

Static random access memory with data controlled power supply

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Hsinchu, Taiwan

Wei Hwang