Phison Electronics Corporation

Princeton Technology Corporation

Hewlett-packard Development Company, L.p.

Strong Fortress Tool Co., Ltd.

Other

Lite-on It Corporation

Wei Hung Lin

Yu-Cheng Hsu

Yu-Siang Yang

Szu-Wei Chen

An-Cheng Liu

Kuo-Hsin Lai

Shih-Jia Zeng

Kuo-Yi Cheng

Tien-Ching Wang

Yu-Hsiang Lin

Shao-Wei Yen

Siu-Tung Lam

Hsiao-Yi Lin

Po-Cheng Su

Chun-Yen Chang

Chih-Wei Wang

Lih Yuarn Ou

Tsai-Hao Kuo

Yu-Heng Liu

Kiang-Giap Lau

Chun-Wei Tsao

Riichiro Shirota

Chih-Kang Yeh

An-Cin Li

Nina Mitiukhina

Chun-Hsi Lai

Ting-Chien Zhan

Chen-An Hsu

Po-Hao Chen

Chen Yang Tang

Jian Ping Syu

Li-Chun Liang

Xiang Ma

Simon Wong

Hao-Zhi Lee

Chun-Hu Cheng

Tai Hsiang Chen

Yu-Chien Chiu

Kim-Hon Wong

Chi-Heng Yang

Cheng-Long Low

Tzung-Lin Wu

Yung Ming Lee

Hung Sung Pan

Yu Ting Tseng

Ryan Lee

Carl Chang

Yi Fan Shih

Yi-Fang Chang

Chien Liu

Shi-Chieh Hsu

Yao-Hsuan Li

Chun Teng Cheng

Hung-Chun Lin

Jia-Fan Chien

Hoe-Hong Lim

The present disclosure provides a memory management method, a memory storage apparatus and a memory control circuit unit. The method includes: performing a first operation on a plurality of physical units to obtain a quality estimation parameter corresponding to the physical units; establishing a check list according to the quality estimation parameter, wherein the check list records index information of a first physical unit among the physical units, and a number of the first physical unit is less than a total number of the physical units; and in response to a default condition being satisfied, performing a status scanning on the first physical unit according to the index information in the check list.

Memory management method, memory storage apparatus and memory control circuit unit

A method of writing data, including: obtaining a write instruction; writing a first data of write data to a target physical unit in a target word line of a plurality of word lines in accordance with the write instruction; after writing the first data, when the target word line has one or more empty physical units arranged after the target physical unit, selecting one or more further target physical unit respectively located in one or more further target word lines; and writing second data connected after the first data in the write data to the selected further target physical units, wherein the one or more further target word lines are arranged after the target word line.

Data writing methods, memory storage device and memory control circuit unit

A data storage method, a host system, and a data storage system are disclosed. The method includes the following. An artificial intelligence (AI) model is executed. First data to be stored to a memory storage device is obtained. In response to the first data being generated by the AI model, second data is generated according to the first data, in which the second data includes the first data, and a data amount of the second data is greater than a data amount of the first data. A first write command is sent to the memory storage device according to the second data, so as to instruct the memory storage device to store the second data.

Data storage method, host system and data storage system

A memory operation method, a memory storage device, and a memory control circuit unit are disclosed. The memory operation includes following steps. First data is received from a host system. The first data is stored into a first physical unit which is mapped to a first logical unit. In a first operation mode, a target calculation is performed based on the first data and second data stored in a second physical unit to obtain third data, and the third data is different from the first data. The third data is stored into a third physical unit which is also mapped to the first logical unit. The third data is transmitted to the host system.

Memory operation method including performing target calculation in memory storage device, memory storage device and memory control circuit unit

A data accessing method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a codeword stored in a physical programming unit, and calculating a bit change ratio of a bit value change in dummy data included in the codeword; adjusting a read voltage level or a log likelihood ratio according to the bit change ratio; and performing a decoding operation on the codeword by using the adjusted read voltage level or the adjusted log likelihood ratio.

Method for adjusting a read voltage level or log likelihood ratio of a memory based on a calculated bit change ratio, memory controlling circuit unit, and memory storage device

A memory management method, a memory storage apparatus and a memory control circuit unit are disclosed. The method includes: sending a plurality of read command sequences including a first read command sequence and a second read command sequence, and the first read command sequence is configured to instruct a performing of a first read operation on a first physical unit of a rewritable non-volatile memory module, and the second read command sequence is configured to instruct a performing of a second read operation on the first physical unit; determining a system parameter according to a time interval between a first read time point corresponding to the first read operation and a second read time point corresponding to the second read operation; and instructing the rewritable non-volatile memory module to perform a specific operation according to the system parameter.

A voltage calibration method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: reading first data from a first physical unit using a first read voltage level and reading second data from at least one second physical unit using a second read voltage level; obtaining count information reflecting a total number of memory cells meeting a default condition in the first physical unit and the at least one second physical unit according to the first data and the second data; and calibrating the first read voltage level according to the count information.

Voltage calibration method, memory storage device and memory control circuit unit

A voltage prediction method, a memory storage device and a memory control circuit unit are disclosed. The method includes: reading a plurality of memory cells in a rewritable non-volatile memory module by using a first read voltage level to obtain count information, and the first read voltage level is configured to distinguish a first state and a second state adjacent to each other in a threshold voltage distribution of the memory cells, and the count information reflects a total number of first memory cells meeting a target condition among the memory cells; and predicting a second read voltage level according to the count information, and the second read voltage level is configured to distinguish a third state and a fourth state adjacent to each other in the threshold voltage distribution.

Voltage prediction method, memory storage device and memory control circuit unit

An example of the present disclosure includes a packaging box, comprising a first section including a first aperture to receive a portion of a writing device, and a second section including a second aperture to receive a remainder of the writing device. The packaging box further includes a hinge mechanism coupling the first section to the second section, wherein the first section and second section are rotatable about the hinge mechanism. The packaging box also includes a tip remover including a surface to remove a tip of the writing device responsive to application of a force.

Writing device packaging boxes

A decoding method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending at least one read command sequence instructing to read a first physical unit in a rewritable non-volatile memory module; receiving response data from the rewritable non-volatile memory module, wherein the response data includes a plurality of identification bits, and the plurality of identification bits reflect a voltage variation of a first bit line where a first memory cell in the first physical unit is located during a discharge process; determining a decoding parameter corresponding to the first memory cell according to the plurality of identification bits; and decoding data read from the first memory cell according to the decoding parameter.

Decoding method, memory storage device and memory control circuit unit

A read voltage adjustment method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending a write command sequence instructing to program a plurality of first memory cells in a rewritable non-volatile memory module; sending a first read command sequence instructing to read the programmed first memory cells using a first read voltage level to obtain first count information; obtaining first compensation information corresponding to the first read voltage level, wherein the first compensation information reflects a deviation in evenly programming the first memory cells to a plurality of states; and adjusting the first read voltage level according to the first count information, the first compensation information, and default count information corresponding to the first read voltage level.

Read voltage adjustment method, memory storage device and memory control circuit unit

A data reading method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: receiving a read command from a host system, and the read command instructs reading data from at least one logical unit, and the logical unit is mapped to a first physical unit; obtaining state information of at least two neighboring memory cells in the first physical unit; determining an electrical parameter offset value corresponding to the neighboring memory cells according to the state information; and sending a read command sequence according to the electrical parameter offset value, and the read command sequence instructs reading the first physical unit based on at least one electrical parameter, and the electrical parameter is controlled by the electrical parameter offset value.

Data reading method, memory storage device, and memory control circuit unit

An exemplary embodiment of the invention provides a read voltage control method for a rewritable non-volatile memory module. The method includes: sending a first read command sequence which instructs a reading of a plurality of first memory cells by using a first voltage level to obtain first data; obtaining first adjustment information of a read voltage according to the first data and a channel parameter of the first memory cells, and the channel parameter reflects a channel status of the first memory cells; and adjusting a voltage level of the read voltage from the first voltage level to a second voltage level according to the first adjustment information.

Read voltage control method, memory storage device and memory control circuit unit

A read voltage level correction method, a memory storage device, and a memory control circuit unit are provided. The method includes: using a first read voltage level as an initial read voltage level to perform a first data read operation on a first physical unit among multiple physical units to obtain a second read voltage level used to successfully read the first physical unit; recording association information between the first read voltage level and the second read voltage level in a transient look-up table; and performing a second data read operation according to a read level tracking table and the association information recorded in the transient look-up table.

Read voltage level correction method, memory storage device, and memory control circuit unit

A decoding method, a memory storage device and a memory control circuit unit are disclosed. The method includes: activating a decoding circuit which supports a plurality of decoding modes each corresponding to a threshold value, wherein a distribution of the threshold value corresponds to error correction abilities of the decoding modes; reading first data from a rewritable non-volatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode among the decoding modes according to a relative numerical relationship between the decoding parameter and the threshold value.

Growing community of inventors

Hsinchu, Taiwan

Wei Hung Lin