Taiwan Semiconductor Manufacturing Comp. Ltd.

Phison Electronics Corporation

Unimicron Technology Corporation

Phoenix Precision Technology Corporation

Wei-Hung Lin

Ming-Da Cheng

Chung-Shi Liu

Kuei-Wei Huang

Chih-Wei Lin

Meng-Tse Chen

Chen-Hua Douglas Yu

Hui-Min Huang

Hsiu-Jen Lin

Chih-Fan Huang

Mirng-Ji Lii

Chun-Cheng Lin

Wei-Yu Chen

Wen-Hsiung Lu

Yu-Peng Tsai

Chang-Jung Hsueh

Ching-Hua Hsieh

Yi-Da Tsai

Yu-Hsiang Hu

Bor-Ping Jang

Chen-Shien Chen

Hung-Jui Kuo

Yu-min Liang

Ai-Tee Ang

Tsai-Tsung Tsai

Chang-Chih Chen

Kai Jun Zhan

Cheng-Ting Chen

Yu-Chih Liu

Jing Ruei Lu

Hung-I Chung

Wan-Yu Chiang

Cheng-Ping Lin

Kuo-Chung Yee

Ming-Che Ho

Chun-Hui Yu

Sheng-Hsiang Chiu

Sheng-Feng Weng

Hsien-Liang Meng

Chen-En Yen

Jeng-Nan Hung

Kuo-Ching Hsu

Sheng-Yu Wu

Yu-Min Liang

Ching-Hui Chen

Yung-Sheng Lin

Cheng Jen Lin

Chin Wei Kang

Chun-Feng Lee

Lin-Wei Wang

Hung-Yi Chung

Cheng-Nan Lin

Yu-Ting Tseng

Chih Chun Chiu

Hao-Yi Tsai

Po-Hao Tsai

Kai-Chiang Wu

Ching-Wen Hsiao

Chao-Wen Shih

Ming-Kai Liu

Hsuan-Ting Kuo

Hsu-Lun Liu

Yun-Chieh Chen

Cheng-Jen Lin

Kai-Jun Zhan

Chin-Wei Kang

Zao-Kuo Lai

Jimmy Liang

Kuan-Liang Lai

Chien-Chun Wang

Yu-Hsiang (James) Hu

Chun-Lung Jao

Hsien-Sheng Tsao

Yen Wei Chang

Ching-Shi Liu

A semiconductor package includes a package substrate including an upper surface layer including a first surface area having a first surface roughness, and a second surface area having a second surface roughness less than the first surface roughness, and an interposer module mounted on the upper surface layer of the package substrate in the second surface area. The semiconductor package may also include an interposer including an upper surface layer including a first surface area having a first surface roughness, and a second surface area having a second surface roughness less than the first surface roughness. The semiconductor package may also include an printed circuit board substrate including an upper surface layer including a first surface area having a first surface roughness, and a second surface area having a second surface roughness less than the first surface roughness.

Semiconductor package including a surface with a plurality of roughness values and methods of forming the same

In a method of forming a heat dissipating structure for a semiconductor chip, a soldering material is disposed on a top surface of the semiconductor chip. A first region of metal plating is formed on a surface of a lid. The first region has a first width and a first length. The first width is larger than a second width of the top surface of the semiconductor chip and the first length is larger than a second length of the top surface of the semiconductor chip. The lid is placed over the semiconductor chip so that the first region of metal plating of the lid is disposed over the soldering material to bond the lid to the semiconductor chip by a soldering material layer having an inverted trapezoidal shape between the lid and the top surface of the semiconductor chip.

Inverted trapezoidal heat dissipating solder structure and method of making the same

A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.

Chip structure and method for forming the same

A semiconductor package includes a package substrate a package substrate including: a substrate core; an upper redistribution layer disposed on a first side of the substrate core; and a lower redistribution layer disposed on an opposing second side of the substrate core; a semiconductor device vertically stacked on and electrically connected to the package substrate; and an upper reinforcement layer embedded in the upper redistribution layer between the semiconductor device and the substrate core, the upper reinforcement layer having a Young's modulus that is higher than a Young's modulus of the upper redistribution layer.

Semiconductor package including reinforcement structure and methods of forming the same

A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.

Semiconductor die including stress-resistant bonding structures and methods of forming the same

According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.

Substrate and package structure

A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.

Semiconductor bonding structures and methods

A method includes forming a reconstructed package substrate, which includes placing a plurality of substrate blocks over a carrier, encapsulating the plurality of substrate blocks in an encapsulant, planarizing the encapsulant and the plurality of substrate blocks to reveal redistribution lines in the plurality of substrate blocks, and forming a redistribution structure overlapping both of the plurality of substrate blocks and encapsulant. A package component is bonded over the reconstructed package substrate.

Packages including multiple encapsulated substrate blocks and overlapping redistribution structures

An apparatus for forming a package structure is provided. The apparatus includes a processing chamber for bonding a first package component and a second package component. The apparatus also includes a bonding head disposed in the processing chamber. The bonding head includes a plurality of vacuum tubes communicating with a plurality of vacuum devices. The apparatus further includes a nozzle connected to the bonding head and configured to hold the second package component. The nozzle includes a plurality of first holes that overlap the vacuum tubes. The nozzle also includes a plurality of second holes offset from the first holes, wherein the second holes overlap at least two edges of the second package component. In addition, the apparatus includes a chuck table disposed in the processing chamber, and the chuck table is configured to hold and heat the first package component.

Apparatus and method for forming a package structure

In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.

Advanced info POP and method of forming thereof

A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.

Semiconductor device, semiconductor package, and methods of manufacturing the same

Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.

Package structure and method of forming the same

A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate. The semiconductor device structure includes a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate. The semiconductor device structure includes an upper conductive via between the conductive pillar and the interconnection structure. A center of the upper conductive via is laterally separated from a center of the protruding portion by a first distance. The semiconductor device structure includes a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via. A center of the lower conductive via is laterally separated from the center of the protruding portion by a second distance that is shorter than the first distance.

Structure and formation method of semiconductor device with conductive bumps

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Xinfeng, China

Wei-Hung Lin