Yangtze Memory Technologies Co., Ltd.

Wuhan Tianma Micro-Electronics Co., Ltd

Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.

Mediatek Singapore Pte. Ltd.

Huazhong University of Science and Technology

Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.

Central China Normal University

Chang Jiang River Scientific Research Institute

Nanjing Natinefy Pharmatech Co., Ltd.

Wuhan Novaffey Science & Technology Co., Ltd.

Shijiazhuang No. 4 Pharmaceutical Co., Ltd.

Wei Huang

Yangzhao Ma

Zhongjie Zhang

Qin Yue

Lu Xiao

Chunyuan Hou

Tianxu Zhang

Kuihua You

Li Xiang

Jun Zhou

Xueqing Huang

Zheng Wang

Qigui Yang

Peng Sun

Kang Li

Guangfu Yang

Heng Yao

Sufei Fan

Yimeng Chen

Qiong Zhan

Cong Luo

Qinyuan Zhang

Ruxin Wei

Hualong Wu

Zuming Liu

Kaiwei Cao

Zhengtao Li

Zhenghua Huang

Ming Yang

Mingshu Wang

Duan Chen

QingYuan Yang

WenGang Duan

YuFang Ni

Jaehun Yang

Huiqun Cao

Fengxiang Gao

Chan Wang

Xing Zhou

Peiliang Zhao

Ning Zhang

Yongyong Wang

Hongchuang Xu

Linsheng Zhuo

The present disclosure provides a high voltage (HV) switch system for a memory device that includes a first switch configured to transfer a boost voltage during a first time period to a first set of selected word lines or a second set of selected word lines of the memory device; a second switch configured to transfer a target regulated voltage during a second time period to the first set of the selected word lines when programming a first set of memory cells coupled to the first set of the selected word lines; and a third switch configured to transfer the target regulated voltage during the second time period to the second set of the selected word lines that is different from the first set of word lines when programming a second set of memory cells coupled to the second set of the selected word lines.

High voltage switches for NAND flash memory

Examples of the present application disclose a memory, a storage system and an electronic product. The memory comprises a control circuit, a voltage loading circuit, a first driver, and a second driver. The voltage loading circuit, in response to a block selection signal received by a control terminal, is configured to load a first voltage to a control terminal of the first driver through a first output terminal, and load a second voltage to a control terminal of the second driver through a second output terminal. Because starting voltages may be loaded by different output terminals, all the drivers do not share the same starting voltage any longer, and performance degradation caused by a tunneling effect is avoided. Therefore, based on the memory provided by the examples of the present application, the performance degradation of various drivers can be improved.

Memory with separate drivers for word lines and select gates

Provided are a display panel, a preparation method, and a display device. The display panel includes a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels. The plurality of third sub-pixels forms a first virtual trapezoid, and one of the plurality of first sub-pixels is located inside the first virtual trapezoid. The plurality of first sub-pixels and the plurality of second sub-pixels form a second virtual trapezoid, and one of the plurality of third sub-pixels is located inside the second virtual trapezoid. The first virtual trapezoid includes a first long side, a first oblique side, a first short side, and a second oblique side. The second virtual trapezoid includes a second long side, a third oblique side, a second short side, and a fourth oblique side.

Display panel, preparation method and display device

Provided is a laboratory experiment system including an upstream reservoir. A main river channel is connected to a water outlet of the upstream reservoir. A barrier dam is built up in the main river channel. Uneroded dam bodies are constructed on two side surfaces of the barrier dam. A branch river channel extends on a surface of the barrier dam. A material hopper is connected to a feed inlet of the branch river channel. River banks are constructed on outer sides of the uneroded dam bodies. The feed inlet is docked with a descending conveyor belt. A feeding end of the descending conveyor belt is docked with an ascending conveyor belt. A discharge end of the material hopper defines a bottom hole. The bottom hole is connected to a material pipe. A discharge end of the material pipe corresponds to an inner side of the ascending conveyor belt.

Laboratory experiment system for breaching of debris-typed barrier dam

A display panel, a display device, and an evaporation device are provided. The display panel includes a plurality of pixel units arranged in an array. Each pixel unit includes four first sub-pixels, two second sub-pixels, and two third sub-pixels. Centers of the two second sub-pixels and centers of the two third sub-pixels form a virtual isosceles trapezoid. The two second sub-pixels are located on both ends of a diagonal of the virtual isosceles trapezoid, and the two third sub-pixels are located on both ends of another diagonal of the virtual isosceles trapezoid. Centers of the four first sub-pixels form a virtual quadrilateral. An interior of the virtual quadrilateral includes one second sub-pixel of the two second sub-pixels, and an interior of the virtual isosceles trapezoid includes one first sub-pixel of the four first sub-pixels.

Display panel, display device, and evaporation device

Semiconductor structure, comprising a memory-array unit comprising: a substrate, a memory array disposed on the substrate, and a first bonding region disposed around the memory array. The memory array comprises multiple word lines, multiple bit lines, and multiple source lines. The first bonding region comprises a first substrate-connecting bonding region, a first bit-line bonding region, a first word-line bonding region, and a first source-line bonding region. The first substrate-connecting bonding region is configured to connect the substrate electrically to a surface of the memory-array unit, the first bit-line bonding region is configured to connect the bit lines electrically to the surface of the memory-array unit, the first word-line bonding region is configured to connect the word lines electrically to the surface of the memory-array unit, and the first source-line bonding region is configured to connect the source lines electrically to the surface of the memory-array unit.

Three dimensional semiconductor memory structure

This application provides a voice device and a voice interaction method of the voice device. The voice device includes at least two voice modules, and the voice interaction method includes: determining the working statuses of the at least two voice modules, selecting one of the two voice modules to execute voice interaction based on preset principles and the working statuses of the at least two voice modules, and suspending the voice interaction of other voice module(s). This application can solve the problem of conflicts between multiple kinds of voice services in the same voice device.

Voice device and voice interaction method thereof

A memory device includes a memory cell array including memory blocks and a peripheral circuit coupled to the memory cell array. Each memory block includes memory strings each including dummy cells and select transistors, bit lines coupled to the memory strings, select lines including first select lines and second select lines, and one or more dummy word lines. Each select line coupled to the select transistors. The first select lines are closer to the bit lines than the second select lines. Each dummy word line is coupled to the respective dummy cells. The dummy word lines include a first dummy word line adjacent to either the first select lines or the second select lines. The peripheral circuit is configured to apply a turn-on voltage to all the first select lines, and apply a program voltage to the first dummy word line.

Memory device with dummy word line, system and method for programming thereof

A voltage supply circuit includes a temperature compensation circuit and a voltage regulation circuit. The temperature compensation circuit includes a comparator circuit comparing a device temperature value with a reference value to output a comparison result, and a compensation controller circuit receiving the comparison result, a compensation value control signal, and a compensation enable signal, and outputting a voltage control signal according to the comparison result. The voltage regulation circuit receives the voltage control signal and provides a voltage output according to the control signal.

Voltage supply circuits, three-dimensional memory devices, peripheral circuit, and methods for adjusting voltage supply circuit

Wireless microphone receiver

The present disclosure provides a display panel. In the display panel, a first backplate is disposed in a terminal region; a flexible substrate including a first portion is disposed in the terminal region, wherein the first portion is disposed on the first backplate; a portion of a reinforcement layer is disposed on the flexible substrate and located in the terminal region; a first protective layer is disposed on the first portion, wherein the first protective layer and the reinforcement layer are disposed separately; and a second protective layer is disposed on the first protective layer and is connected to the reinforcement layer.

Display panel

Provided are a display panel and a driving method thereof, an array substrate, a display panel, and a display device. The pixel circuit includes a drive circuit, a first initialization circuit, a data write circuit, and a threshold compensation circuit. The control terminal of the drive circuit is electrically connected to a first node. A first terminal of the drive circuit is electrically connected to a second node, and a second terminal of the drive circuit is electrically connected to a third node. A first terminal of the first initialization circuit is electrically connected to a first reference signal terminal, and a second terminal of the first initialization circuit is electrically connected to the third node. The control terminal of the data write circuit is electrically connected to a scanning signal terminal.

Display panel and driving method thereof, array substrate, display panel, and display device

Disclosed are display panel and display device. The display panel includes plurality of pixel repetitive units arranged in array. Each pixel repetitive unit includes two first sub-pixels, two second sub-pixels and four third sub-pixels, and light emitting colors of two first sub-pixels, two second sub-pixels and four third sub-pixels are different. For each pixel repetitive unit, centers of four third sub-pixels constitute first virtual square, one first sub-pixel located inside the first virtual square, and center of the first virtual square doesn't overlap center of one first sub-pixel located inside the first virtual square; and centers of two first sub-pixels and centers of two second sub-pixels constitute first virtual parallelogram, and one third sub-pixel located inside the first virtual parallelogram. The arrangement of the third sub-pixels can reduce display serrated sense of vertical line array and improve display effect of vertical line, thereby improving display effect of display panel.

Display panel and display device

The present invention provides a display, including: a panel including a bending area and two non-bending areas disposed on opposite sides of the bending area; and a first metal sheet and a second metal sheet respectively disposed on the two non-bending areas, wherein an end portion of at least one of the first metal sheet and the second metal sheet close to the bending area has a blunt structure.

Display having a blunt structure

This invention involves the field of biomedicine, and reveals naphthyridine compounds, medical combinations and use thereof. The naphthyridine compounds has the structure as shown by Formula (I), or its stereoisomers, geometric isomers, tautomers, nitrogen oxides, hydrates, solvates, metabolites, pharmaceutically acceptable salts or their prodrugs. The naphthyridine compounds of this invention has anti-tumor efficacy significantly superior to that of prior art. Moreover, the naphthyridine compounds of this invention can treat diseases mediated by protein kinases. 

Naphthyridine compounds, medical combinations and use thereof

Growing community of inventors

Wuhan, China

Wei Huang