Chartered Semiconductor Manufacturing Ltd (corporation)

Wei Hua Cheng

Daniel Yen

Yakub Aliyu

Chit Hwei Ng

Marvin De-Dui Liao

Ding Yi

Tong Boon Lee

Ching-Thiam Chung

Chester Nieh

Lee Yuan Ping

There is a need for adjustable capacitors for use in LC or RC matching networks in micro-circuits. This has been achieved by forming a set of individual capacitors that share a common bottom electrode. The areas of the top electrodes of these individual capacitors are chosen to be in an integral ratio to one another so that they can be combined to produce any capacitance within a range of unit values. For example, if four capacitors whose areas are in the ratio of 5:2:1:1, are provided, then any capacitance in a range of from 1 to 9 can be generated, depending on how the top electrodes are connected. Such connections can be hard-wired within the final wiring level to provide a factory adjustable capacitor or they can be connected through field programmable devices to produce a field programmable capacitor. A process for manufacturing the device is also described.

Adjustable 3D capacitor

A method for forming a via in a damascene process. In one embodiment, the present method comprises depositing a material into a via formed using a damascene process. More particularly, in one embodiment, the material which is comprised of a substantially conformal material which has an etch selectivity with respect to the substrate into which the via is formed. Furthermore, in this embodiment, the material is deposited along the sidewalls and the base of the via. Next, the present embodiment etches material such that the via is formed having a profile conducive to the adherence of overlying material thereto. In this embodiment, the etching of the material is performed without substantially etching the substrate into which the via is formed. In so doing, the present embodiment creates a via in a damascene process which allows for the formation of a metallized interconnect which is substantially free of voids.

Method for forming a via in a damascene process

A process for fabricating a CMOS device in which conductive gate structures are defined self-aligned to shallow trench isolation (STI), regions, without using a photolithographic procedure, has been developed. The process features definition of shallow trench openings in regions of a semiconductor substrate not covered by dummy gate structures, or by silicon oxide spacers located on sides of the dummy gate structures. Filling of the shallow trench openings with silicon oxide, and removal of the dummy gate structures, result in STI regions comprised of filled shallow trench openings, overlying silicon oxide shapes, and silicon oxide sidewall spacers on the sides of the overlying silicon oxide shapes. Formation of silicon nitride spacers on the sides of the STI regions, is followed by deposition of a high k gate insulator layer and of a conductive gate structure, with the conductive gate structure formed self-aligned to the STI regions.

Method of self-aligning a damascene gate structure to isolation regions

A method and apparatus for reducing gouging during via formation. In one embodiment, the present invention is comprised of a method which includes forming an opening into a substrate. The opening is formed extending into the substrate and terminating on at least a portion of a target to which it is desired to form an electrical connection. After the formation of the opening, the present embodiment lines the opening with a liner material. In this embodiment, the liner material is adapted to at least partially fill a portion of the opening which is not landed on the target. The liner material of the present embodiment prevents substantial further etching of the substrate conventionally caused by the opening being at least partially unlanded on the target. Next, the present embodiment subjects the liner material to an etching process such that the liner material is substantially removed from that region of the target where the opening was landed on the target. In this embodiment, liner material residing in the region where the opening is unlanded prevents further gouging of the substrate proximate to the target.

Method for reducing gouging during via formation

A semiconductor wafer carrier fork cover to prevent damage to prevent breakage of the semiconductor wafer carrier forks mounted on a robotic semiconductor wafer transfer system during preventative maintenance procedures is described. A semiconductor wafer carrier fork cover has a lower support unit. The lower support unit will fit onto the base of a robotic semiconductor wafer transfer system. An upper covering unit is integrally attached to the lower support unit and will shield the semiconductor wafer carrier forks during preventive maintenance procedures.

Fork cover for vertical furnace

A float device is disclosed with an improved external surface having an outwardly concave curvature and a plurality of elongated grooves spirally formed on the concave surface. The concave surface provides improved clearance between the float device and the walls of the pipe that it is disposed in. Therefore, the float device is less subject to being lodged or stuck especially in highly viscous liquids. The spiral grooves provide additional passageway and stability by imparting rotational torque to the floating device when measuring flow rates in moving fluids in pipes. In another embodiment, the float device is annular in shape having an inner surface with a curvature and spiral grooves. Same improved effects are obtained as the float device rides up and down a column like a collar in measuring the fluid level or fluid flow rates.

Growing community of inventors

Singapore, Singapore

Wei Hua Cheng