University of California

Tortuga Logic Inc.

Wei Hu

Ryan Kastner

Jason K Oberg

Timothy Sherwood

Armaiti Ardeshiricham

Mohit Tiwari

Disclosed are devices, apparatuses, systems, computer readable media, and methods for improving the security of circuitry designs using HDL code. In one aspect a method is disclosed. the method includes receiving a hardware design language (HDL) representation of a circuit; inserting flow tracking into the HDL representation, wherein the flow tracking adds one or more security labels that are tracked throughout the circuit; and generating an enhanced HDL representation of the circuit, wherein the enhanced HDL representation comprises the HDL representation and the flow tracking, wherein the enhanced representation including the one or more security labels that are tracked throughout the circuit enables a security determination a model for tracking timing-based information flows through HDL code is disclosed. The disclosed technology is used to verify security properties on a variety of equipment including crypto cores, bus architectures, caches and arithmetic modules.

Techniques for improving security of circuitry designs based on a hardware description language

The present disclosure includes systems and methods relating to information flow tracking and detection of unintentional design flaws of digital devices and microprocessor systems. In general, in one implementation, a technique includes: receiving a hardware design specifying an implementation for information flow in a hardware configuration; receiving one or more labels annotating the hardware design; receiving one or more security properties specifying a restriction relating to the one or more labels for implementing an information flow model; generating the information flow model; performing verification using the information flow model, wherein verification comprises verifying whether the information flow model passes or fails against the one of more security properties; and upon verifying that the information flow model passes, determining that an unintentional design flaw is not identified in the hardware design.

Method and system for detecting hardware trojans and unintentional design flaws

A preferred method for providing multi-level security to a gate level information flow receives or specifies a security lattice having more than two security levels. The security lattice defines how security levels relate to each other. A hardware design implementing information flows including flows having security levels specified by the security lattice is received. Logic is created for testing the hardware design in view of the security lattice. A logic function is created based upon the hardware design and the logic for testing to implement the security lattice. Another method receives a hardware design in a hardware description language. At least a portion of the hardware design is synthesized to gate level primitives. Functional component tracking logic supporting more than two-security levels is built from the gate level primitives. Functional components in the hardware design are simulated with the functional component tracking logic.

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La Jolla, CA, United States of America

Wei Hu