Mediatek Corporation

Mediatek Incorporation

Wei-Hsuan Tu

Tse-Hsiang Hsu

Tzung-Hung Kang

Bing-Yu Hsieh

Meng-Hsueh Lin

Chun-Chih Hou

A multiplying digital-to-analog converter includes an operational amplifier (OP-amp) operated under a first power supply voltage and a second power supply voltage; an OP-amp input switch block coupled to a common mode voltage for selectively coupling the common mode voltage to input nodes of the OP-amp, wherein the common mode voltage is substantially equal to the first power supply voltage; a capacitor block coupled to the OP-amp input switch block; a sampling switch block coupled to the input signal for selectively coupling the input signal to the capacitor block; a reference voltage switch block coupled to the capacitor block for selectively coupling the reference signal to the capacitor block; and a feedback switch block coupled between the capacitor block and output nodes of the OP-amp.

Multiplying digital-to-analog converter for high speed and low supply voltage

A reference buffer circuit with high driving capability is disclosed. In which, a buffering stage has a first NMOS transistor and a first PMOS transistor to provide high and low tracking voltages respectively based on a high input voltage and a low input voltage. A first driving stage is driven by the high and low tracking voltages to output a first high output voltage and a first low output voltage. A body of the first PMOS transistor is tied to a first bias voltage lower than a supply voltage for the buffering and first driving stages.

Reference buffer circuit

An analog-to-digital (A/D) conversion device is provided and includes a first A/D conversion stage. The A/D conversion stage includes a first pre-amp unit, first and second latch units, and a first conversion unit. The first pre-amp unit amplifies the analog input data and outputs a first amplified data. The first and second latch units are enabled by first and second latch clock signals to latch the first and second amplified data and generate first and second latched data, respectively. The first pre-amp unit is reset between a time point when the first latch unit is enabled and a time point when the second latch unit is enabled. The first conversion unit receives the analog input data, and the first and second latched data and accordingly generates a first analog output data.

Analog-to-digital conversion devices and analog-to-digital conversion stages thereof

A multiplying digital-to-analog converter includes an operational amplifier (OP-amp) operated under a first power supply voltage and a second power supply voltage; an OP-amp input switch block coupled to a common mode voltage for selectively coupling the common mode voltage to input nodes of the OP-amp, wherein all switches included in the OP-amp input switch block are implemented utilizing PMOS transistors only, and the common mode voltage is substantially equal to the first power supply voltage; a capacitor block coupled to the OP-amp input switch block; a sampling switch block coupled to the input signal for selectively coupling the input signal to the capacitor block; a reference voltage switch block coupled to the capacitor block for selectively coupling the reference signal to the capacitor block; and a feedback switch block coupled between the capacitor block and output nodes of the OP-amp.

A Delta-Sigma DAC and a digital to analog conversion method are provided. A FIR filter receives a shaped digital signal to generate a first current on a first output node, and a second current on a second output node. A current inverter is coupled to the second output node, outputting a reversed current having opposite polarity and identical magnitude of the second current. A current to voltage converter is coupled to the first output node and the output of current inverter, generating an analog signal according to the first and reversed currents. A first current source compensates DC offset for the first current, and a second current source compensates DC offset for the second current. The first and second current sources are implemented by NMOS.

Method and apparatus for digital to analog conversion

Variable gain amplifiers with wider linear range are provided, in which first and second loads are coupled to a power voltage, and a transconductor cell comprises first and second transistors, a gain control transistor, and first and second current sources. The first and second transistors comprise control terminals receiving a set of input signals, first terminals coupled to the first and second loads respectively, and second terminal coupled to first and second nodes respectively. The first and second current sources are coupled between the first node and a first voltage and between the second node and the first voltage respectively. The first gain control transistor is coupled between the first node and second node, receiving a gain control voltage, in which the grain control transistor has a threshold voltage lower than that of the first and second transistors.

Variable gain amplifiers

A method for tuning a filter is provided. The method includes: enabling a VCO circuit, wherein at least a portion of the VCO circuit is selected from the filter; generating an oscillation signal by the VCO circuit according to a driving signal; comparing the oscillation signal with a reference signal and generating a comparison result; and adjusting the driving signal according to the comparison result.

Apparatus and method for tuning center frequency of a filter

A tuning method and a tuning apparatus for tuning a filter are disclosed. The tuning method includes: configuring the filter as a VCO; utilizing the VCO to generate an oscillation signal according to a driving signal; comparing a frequency of the oscillation signal with a reference frequency to generate a comparison result; converting the comparison result into the driving signal in order to establish a feedback mechanism. Therefore, the inner components such as the gm and capacitance inside the VCO are completely tuned when the VCO generates an oscillation signal having a wanted frequency. Since the VCO is inside the filter and the components of the filter and the VCO are similar, the driving signal can be utilized to make the filter operate in a desired center frequency under a well-designed relationship between the frequency of the oscillation signal and the center frequency.

A Delta-Sigma DAC is provided, comprising an interpolator, a Delta-Sigma modulator, a FIR filter and an analog filter. The interpolator oversamples a n-bit digital signal to generate a n-bit oversampled signal. The Delta-Sigma modulator coupled to the output of interpolator shapes the n-bit oversampled digital signal to generate a shaped digital signal. The FIR filter coupled to the Delta-Sigma modulator filters the shaped digital signal to generate an analog audio signal. The analog filter coupled to the FIR filter amplifies the analog audio signal to generate a audible signal.

Delta-Sigma DAC

An automatic gain control apparatus receiving an analog signal and outputting a digital signal includes a variable gain amplifier, an A/D converter, and a feedback circuit. The variable gain amplifier amplifies the analog signal with a gain. The A/D converter converts the amplified analog signal to the digital signal. The feedback circuit includes an amplitude level detector, a range detector, and a gain controller. The amplitude level detector generates a first amplitude level and a second amplitude level in response to the digital signal. The range detector generates an adjustment signal in response to the first amplitude level and the second amplitude level. The gain controller adjusts a gain control level for the variable gain amplifier in response to the adjustment signal.

Automatic gain control apparatus

The present invention discloses a multiphase waveform generator capable of performing phase calibration, and a related phase calibration method. The disclosed multiphase waveform generator includes a multiphase waveform generating module and a calibrating module. The multiphase waveform generating module receives an input signal and shifts edges of the input signal by a delay time according to a delay parameter to generate a phase-modified signal. The calibrating module is coupled to the multiphase waveform generating module for calibrating the delay time to reduce a difference between a characteristic value of the phase-modified signal and an expected value, which is calculated according to the delay parameter and characteristic values of a first and a second predetermined periodic signal.

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Hsinchu, Taiwan

Wei-Hsuan Tu