Mstar Semiconductor, Inc.

Via Technologies, Inc.

Wei-Hsiang Hong

Ying-Chieh Tu

Yao-Chun Su

Chia Chiang Ho

Cheng-Yu Hsieh

Chih-Kuo Kao

Yu-Cheng Lin

Yu-Hsiang Tseng

Peter Chia

Wan-Chan Hu

An image processing device that converts original image data to target image data is provided. The image processing device includes: a static random access memory (SRAM); an image scaling circuit that generates scaled image data according to the original image data and stores the scaled image data to the SRAM; and a video encoding circuit that accesses the scaled image data from the SRAM and encodes the accessed scaled image data to generate the target image data. The target image data corresponds to an image frame. A part of the target image data is intra frame data encoded by an intra frame compression method, and the other part of the target image data is predicted frame data encoded by a predicted frame compression method.

Image processing device and method thereof

An image processing method is provided. The method is for calculating a first weighted sum of absolute difference (WSAD) of a first search window and a corresponding first target window, and a second WSAD of a second search window and a corresponding second target window. The first and second search windows have a common matching window, and the first and second target windows have a common target block. The method includes: a) calculating a plurality of absolute differences of the common matching window and the common target block; b) determining a first weight coefficient group and a second weight coefficient group; and c) summing up products of multiplying the absolute differences by the first weight coefficient group to generate the first WSAD, and summing up products of multiplying the absolute differences by the second weight coefficient group to generate the second WSAD.

Image processing circuit and method thereof

A data access method applicable on an electronic apparatus is provided. The electronic apparatus comprises a control unit, a first storage apparatus, and a second storage apparatus. The method comprising: storing a first part of data and a second part of data of a data group in the first storage apparatus and the second storage apparatus, respectively; and selectively accessing the first storage apparatus and the second storage apparatus via different data paths for the first part of data and the second part of data, wherein access speed to the first storage apparatus is different from access speed to the second storage apparatus.

Data accessing method and electronic apparatus utilizing the data accessing method

A motion estimation method applied to a video signal having a first frame and a second frame is provided. The motion estimation method includes: capturing a matching window from the first frame; capturing a searching area from the second frame, the searching area including a plurality of searching blocks each having a size equal to that of the matching window; selecting one of the searching blocks; calculating a difference between pixel data of the selected searching blocks and pixel data of the matching window, so as to obtain N total differences corresponding to N searching blocks; and determining a motion vector corresponding to the matching window according to the N total differences.

Motion estimation method

A request scheduling method is provided in a request accessing system having a processing unit, an upstream unit coupled to the processing unit, a downstream unit coupled to the processing unit and the upstream unit, and at least one endpoint device coupled to the upstream unit and the downstream unit, wherein the endpoint device asserts at least one request to the upstream unit. The request scheduling method includes: transmitting the request to a processing unit while the request is a non-peer-to-peer request, and transmitting the request to a downstream unit while the request is a peer-to-peer request; wherein if the request is a peer-to-peer and posted request and there is a previous asserted request which is peer-to-peer and non-posted request and the previous asserted request has a latency exceeds a predetermined time, transmitting the request earlier than the previous asserted request to the downstream unit.

Method and system for request accessing and scheduling

A chip for use with both a high-speed bus and a low-speed bus in a computer system includes a test control unit recorded therein a preset address data for determining a transmission path of an external signal in a test mode of the chip; an upstream control unit for transmitting the external signal to the high-speed bus in a normal operation mode of the chip, coupled to the test control unit for optionally receiving the external signal in the test mode; and a downstream control unit for transmitting the external signal to the low-speed bus in the normal operation mode of the chip, coupled to the test control unit for optionally receiving the external signal in the test mode.

Growing community of inventors

Taipei, Taiwan

Wei-Hsiang Hong