Taiwan Semiconductor Manufacturing Comp. Ltd.

Wei-Hao Wu

Zhi-Chang Lin

Chih-Hao Wang

Jia-Ni Yu

Huan-Chieh Su

Kai-Chieh Yang

Ting-Hung Hsu

Zhiqiang Wu

Ru-Gun Liu

Chia-Hao Chang

Yu-Ming Lin

Li-Te S Lin

Jia-Chuan You

Ken-Ichi Goto

Kuo-Cheng Chiang

Teng-Chun Tsai

Chung-Wei Hsu

Yi-Hsiung Lin

Po-Chin Chang

Pinyen Lin

Yung-Sung Yen

Wei-Liang Lin

Yu-Tien Shen

Chia-Wen Liu

Ya-Wen Yeh

Ching-Wei Tsai

Tsu-Hsiu Perng

Dhanyakumar Mahaveer Sathaiya

Kuan-Lun Cheng

Chih-Ming Lai

Jiann-Tyng Tzeng

Chih-Liang Chen

Charles Chew-Yuen Young

Lung-Kun Chu

Tsung-Hsing Yu

Lei-Chun Chou

Yuan-Chen Sun

Kuo-Cheng Ching

Mao-Lin Huang

Wen-Hsing Hsieh

Kuei-Shun Chen

Ya Hui Chang

Tzer-Min Shen

Shih-Chun Huang

Ke-Jing Yu

Chia-Hao Kuo

Jhon Jhy Liaw

Carlos H Diaz

Jean-Pierre Colinge

Wai-Yi Lien

Yi-Hsun Chiu

Chia-Wei Su

Mahaveer Sathaiya Dhanyakumar

Kam-Tou Sio

Chun-Hsiung Lin

Hung-Chang Sun

Shih-Ting Hung

Yi-Hsuan Hsiao

Hsiang-Pi Chang

Inez Fu

Gloria Wu

Meikei Ieong

The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes forming a hard mask layer over a substrate, the substrate having one or more regions to receive a treatment process, forming a resist layer over the hard mask layer, patterning the resist layer to form a plurality of openings in the resist layer, each of the openings free of concave corners, performing an opening expanding process to enlarge at least one of the openings in the resist layer, transferring the openings in the resist layer to the hard mask layer, and performing the treatment process to the one or more regions in the substrate through the openings in the hard mask layer.

Pattern fidelity enhancement

A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

Liner for a bi-layer gate helmet and the fabrication thereof

In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.

Method of manufacturing semiconductor devices using directional process

A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first source and a first drain separated by a first distance, a first semiconductor structure disposed between the first source and first drain, a first gate electrode disposed over the first semiconductor structure, and a first dielectric structure disposed over the first gate electrode. The first dielectric structure has a lower portion and an upper portion disposed over the lower portion and wider than the lower portion. The second transistor includes: a second source and a second drain separated by a second distance greater than the first distance, a second semiconductor structure disposed between the second source and second drain, a second gate electrode disposed over the second semiconductor structure, and a second dielectric structure disposed over the second gate electrode. The second dielectric structure and the first dielectric structure have different material compositions.

Method and device for forming metal gate electrodes for transistors

The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Metal rail conductors for non-planar semiconductor devices

A method of fabricating a device on a substrate includes doping a channel region of the device with dopants. The method further includes growing an undoped epitaxial layer over the channel region, wherein growing the undoped epitaxial layer comprises deactivating dopants in the channel region to form a deactivated region. The method further includes forming a gate structure over the deactivated region.

Method of dopant deactivation underneath gate

A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.

Reducing pattern loading in the etch-back of metal gate

A semiconductor device includes an active fin disposed on a substrate, a gate structure, and a pair of gate spacers disposed on sidewalls of the gate structure, in which the gate structure and the gate spacers extend across a first portion of the active fin, and a bottom surface of the gate structure is higher than a bottom surface of the gate spacers.

Semiconductor device and method fabricating the same

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate; a first conductive feature and a second conductive feature disposed on the semiconductor substrate; and a staggered dielectric feature interposed between the first and second conductive feature. The staggered dielectric feature includes first dielectric layers and second dielectric layers being interdigitated. The first dielectric layers include a first dielectric material and the second dielectric layers include a second dielectric material being different from the first dielectric material.

Semiconductor structure with staggered selective growth

Provided are FinFET devices and methods of forming the same. A dummy gate having gate spacers on opposing sidewalls thereof is formed over a substrate. A dielectric layer is formed around the dummy gate. An upper portion of the dummy gate is removed and upper portions of the gate spacers are removed, so as to form a first opening in the dielectric layer. A lower portion of the dummy gate is removed to form a second opening below the first opening. A metal layer is formed in the first and second openings. The metal layer is partially removed to form a metal gate.

FinFET devices and methods of forming the same

A semiconductor device includes a semiconductor substrate; a plurality of channel regions, including a p-type channel region and an n-type channel region, disposed over the semiconductor substrate; and a gate structure. The gate structure includes a gate dielectric layer disposed over the plurality of channel regions and a work function metal (WFM) structure disposed over the gate dielectric layer. The WFM structure includes an n-type WFM layer over the n-type channel region and not over the p-type channel region and further includes a p-type WFM layer over both the n-type WFM layer and the p-type channel region. The gate structure further includes a fill metal layer disposed over the WFM structure and in direct contact with the p-type WFM layer.

Gate structure and patterning method

A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.

Methods of cutting metal gates and structures formed thereof

A semiconductor device includes a first device formed over a substrate. The first device includes a first device formed over a substrate, and the first device includes a first gate stack structure encircling a plurality of first nanostructures. The semiconductor device includes a first epitaxy structure wrapping an end of one of the first nanostructures, and a second device formed over the first device, wherein the second device includes a second gate stack structure encircling a plurality of second nanostructures. The semiconductor device includes a second epitaxy structure wrapping an end of one of the second nanostructures, and the second epitaxy structure is directly above the first epitaxy structure.

Semiconductor device and manufacturing method thereof

Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.

Integrated circuits with gate cut features

Growing community of inventors

Hsinchu, Taiwan

Wei-Hao Wu