Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Chang Chun Petrochemical Co., Ltd.

Chang Chun Plastics Co., Ltd.

Dairen Chemical Corporation

Wei Hao Lu

Li-Li Su

Chien-I Kuo

Chii-Horng Li

Wei Te Chiang

Yi-Fang Pai

Yee-Chia Yeo

Tzu-Ching Lin

Wei-Yang Lee

Cheng-Wen Cheng

Chia-Pin Lin

Yen-Ting Chen

Bo-Yu Lai

Chia-Ling Chan

Jyun-Chih Lin

Roa-Pu Shen

Shao-Fu Fu

Po-Yu Lin

Wei-Han Fan

Wei-Min Liu

Tzu-Hua Chiu

Kuan-Hao Cheng

LI-Li Su

Tung-Yu Wang

An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.

FETS and methods of forming FETS

A semiconductor device includes: a first fin and a second fin extending from a substrate and an epitaxial source/drain region. The epitaxial source/drain region includes a first portion grown on the first fin and a second portion grown on the second fin, and the first portion and the second portion are joined at a merging boundary. The epitaxial source/drain region further includes a first subregion extending from a location level with a highest point of the epitaxial source/drain region to a location level with a highest point of the merging boundary, a second subregion extending from the location level with the highest point of the merging boundary to a location level with a lowest point of the merging boundary, and a third subregion extending from the location level with the lowest point of the merging boundary to a location level with a top surface of an STI region.

Source/drain regions of semiconductor devices and methods of forming the same

A semiconductor device includes a fin-shape base protruding from a substrate, channel structures suspended above the fin-shape base, a gate structure wrapping around each of the channel structures, a source/drain (S/D) epitaxial feature abutting the channel structures and directly above a top surface of the fin-shape base, inner spacers interposing the S/D epitaxial feature and the gate structure, and a dielectric layer disposed vertically between the top surface of the fin-shape base and a bottom surface of the S/D epitaxial feature.

Semiconductor device with leakage current suppression and method for forming the same

A method of forming a semiconductor includes forming a first recess in a first semiconductor fin protruding from a substrate and forming a second recess in a second semiconductor fin protruding from the substrate first semiconductor fin and forming a source/drain region in the first recess and the second recess. Forming the source/drain region includes forming a first portion of a first layer in the first recess and forming a second portion of the first layer in the second recess, forming a second layer on the first layer by flowing a first precursor, and forming a third layer on the second layer by flowing a second precursor, the third layer being a single continuous material.

Source/drain device and method of forming thereof

A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.

Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.

Source and drain engineering process for multigate devices

FETs and methods of forming FETs

A device includes a fin extending from a substrate; a gate stack over and along sidewalls of the fin; a gate spacer along a sidewall of the gate stack; an epitaxial source/drain region in the fin and adjacent the gate spacer, the epitaxial source/drain region including a first epitaxial layer on the fin, the first epitaxial layer including silicon and arsenic; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin; and a contact plug on the second epitaxial layer.

Semiconductor device and method of manufacture

FinFET having a non-faceted top surface portion for a source/drain region

The present disclosure provides antransformant and a method for producing itaconate using thetransformant.

transformant for producing itaconate and uses thereof

The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.

Semiconductor device source/drain region with arsenic-containing barrier region

The present invention provides an engineered cyanobacterium, comprising at least one plasmid selected from three novel pathways to produce acetate, which can convert atmospheric carbon dioxide as a raw material into acetate. The present invention also constructs the expression plasmid for three different transporters specific to acetate to be expressed in cyanobacteria, which comprises putative ABC transporter (AatA), succinate/acetate: proton symporter (SatP) and acetate/glycolate: cation symporter (ActP). Therefore, the engineered cyanobacteria of the present invention can produce 0.58 mg/L to 3.54 mg/L of acetate per hour.

Engineered cyanobacterium and its application for producing acetate

Growing community of inventors

Taoyuan, Taiwan

Wei Hao Lu