Andes Technology Corporation

Mediatek Corporation

Wei-Hao Chiao

Hong-Men Su

Haw-Luen Tsai

Chien-Hung Lin

Zhong-Ho Chen

Chen-Wei Chang

A method for compressing instruction is provided, which includes the following steps. Analyze a program code to be executed by a processor to find one or more instruction groups in the program code according to a preset condition. Each of the instruction groups includes one or more instructions in sequential order. Sort the one or more instruction groups according to a cost function of each of the one or more instruction groups. Put the first X of the sorted one or more instruction groups into an instruction table. X is a value determined according to the cost function. Replace each of the one or more instruction groups in the program code that are put into the instruction table with a corresponding execution-on-instruction-table (EIT) instruction. The EIT instruction has a parameter referring to the corresponding instruction group in the instruction table.

Method for compressing variable-length instructions including PC-relative instructions and processor for executing compressed instructions using an instruction table

A snoop filter for a multi-processor system has a storage device and a control circuit. The control circuit manages at least a first-type entry and at least a second-type entry stored in the storage device. The first-type entry is configured to record information indicative of a first cache of the multi-processor system and first requested memory addresses that are associated with multiple first cache lines each being only available in the first cache. The second-type entry is configured to record information indicative of multiple second caches of the multi-processor system and at least a second requested memory address that is associated with a second cache line being available in each of the multiple second caches.

Snoop filter for multi-processor system and related snoop filtering method

A microprocessor is provided, which includes a processor core and an instruction loop cache. The processor core provides a fetch address of an instruction stream. The fetch address includes a tag and an index. The instruction loop cache receives the fetch address from the processor core. The instruction loop cache includes a cache array and a tag storage. The cache array stores multiple cache entries. Each cache entry includes a tag identification (ID). The cache array outputs the tag ID of the cache entry indicated by the index of the fetch address. The tag storage stores multiple tag values and output the tag value indicated by the tag ID output by the cache array. The instruction loop cache determines whether a cache hit or a cache miss occurs based on a bitwise comparison between the tag of the fetch address and the tag value output by the tag storage.

Microprocessor and method for using an instruction loop cache thereof

A constant data accessing system having a constant pool comprises a computer processor having a constant pool base register, a compiler having a constant pool handler, and an instruction set module having a constant pool instruction set unit. The constant pool base register is configured to store a value of constant pool base address of one or a plurality of subroutines which have constants to be accessed.

Growing community of inventors

Hsinchu, Taiwan

Wei-Hao Chiao