Lattice Semiconductor Corporation

International Business Machines Corporation

Agency for Science, Technology and Research

Wei Han

Fulong Zhang

Warren Juenemann

Sreepada Hegade

Yoshita Yerramilli

Mose Wahlstrom

Joel Coplen

Zheng Chen

Srirama Chandra

Yu Sun

Alshakim Nelson

Amanda Catherine Engler

Loren McLaury

Mu San Zhang

Eric Lee

James L Hedrick

Vijayshankar Raman

Jeannette M Garcia

Yi Yan Yang

Gregory Breyta

Satwant Singh

Daniel Joseph Coady

Lin Qiao

David Lee Rutledge

Ravindar Mohan Lall

Robert J Ono

Ming Hui Ding

Julian M W Chan

Mark Everhard

Gordon Hands

John Gordon Hands

Rudy J Wojtecki

Inderpal Singh Narang

Ankit Vora

You-Chin Gene Fuh

Fen-Ling Lin

Barry Britton

Hareem Tariq Maune

Jye Yng Teo

Shaoqiong Liu

Nathan Green

Kanad Chakraborty

Ying-Lin Chen

Kouhorng Allen Yang

Ravindar Lail

Joel Copien

Jie Qin

Shankar Durgamahanthi

Dan Ratchen

Ravindar Lall

Systems and methods for provisioning secure programmable logic devices (PLDs) are disclosed. An example secure PLD provisioning system includes an external system comprising a processor and a memory and configured to be coupled to a secure PLD through a configuration input/output (I/O) of the secure PLD. The external system is configured to generate a locked PLD comprising the secure PLD based, at least in part, on a request from a secure PLD customer, wherein the request from the secure PLD customer comprises a customer public key; and to provide a secured unlock package for the locked secure PLD. The external system may also be configured to provide an authenticatable key manifest comprising a customer programming key token and a corresponding programming public key associated with the locked secure PLD, wherein the authenticatable key manifest is signed using a programming private key generated by the locked secure PLD.

Key provisioning systems and methods for programmable logic devices

Systems and methods for secure booting of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in a PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in a non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD to the configuration engine. The secure PLD is configured to retrieve a pre-authentication status associated with the configuration image from the NVM, determine or verify the retrieved pre-authentication status associated with the configuration image includes a valid status, and boot the PLD fabric of the secure PLD using the configuration image.

Secure boot systems and methods for programmable logic devices

Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes performing a read operation on a non-volatile memory to obtain a first value. The method further includes comparing the value to a predetermined value to obtain a comparison result. The method further includes determining whether a boot image stored on the non-volatile memory is to be read based at least on the first comparison result. The method further includes performing, based on the determining, a read operation on the boot image to obtain data associated with booting of a device. The method further includes booting the device based at least on the data. Related systems and devices are provided.

Fast boot systems and methods for programmable logic devices

Systems and methods for failure characterization of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD. The secure PLD is configured to receive a failure characterization (FC) command from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O, and to execute the FC command to, at least in part, erase and/or nullify portions of the NVM. The secure PLD may also be configured to boot a debug configuration for the PLD fabric that identifies and/or characterizes operational failures of the secure PLD.

Failure characterization systems and methods for erasing and debugging programmable logic devices

Systems and methods for asset management for secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD. The secure PLD is configured to receive a secure PLD asset access request from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O, and to perform a secure PLD asset update process corresponding to the secure PLD asset access request, where the performing the asset update process is based on a lock status associated with a secure PLD asset corresponding to the secure PLD asset access request.

Asset management systems and methods for programmable logic devices

Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes receiving configuration data associated with a PLD. The PLD includes an array of configuration memory cells including logic block memory cells and input/output (I/O) block memory cells associated with the PLD's logic fabric and I/O fabric, respectively. The method further includes programming a subset of the I/O block memory cells with the configuration data, and providing a wakeup signal to activate functionality associated with a portion of the I/O fabric. The method further includes programming remaining configuration memory cells of the array with the configuration data, where the remaining configuration memory cells include at least a subset of the logic block memory cells. The method further includes providing a wakeup signal to activate functionality associated with at least a portion of the logic fabric. Related systems and devices are provided.

A number of cationic antimicrobial polymers have been synthesized by a condensation polymerization in bulk. The initial polymer formed has backbone tertiary nitrogens, which are subsequently quaternized using a suitable quaternizing agent (e.g., alkyl halide). The cationic polymers include polyamides, polycarbonates, polypolyureas and polyguanidiniums having a cationic repeat unit comprising the quaternary ammonium nitrogen as a backbone nitrogen. The cationic polymers can be active against Gram-negative, Gram-positive microbes, and/or fungi.

Condensation polymers for antimicrobial applications

A thermo-responsive shear-thinning photo-curable composition comprises water, a linear amphiphilic polyether ABA triblock copolymer comprising at least one pendent ene group (*&#x2014;CH&#x2550;CH) capable of undergoing a thiol-ene reaction, a water-soluble crosslinking agent comprising two or more methylenethiol groups (*&#x2014;CHSH), and a photoinitiator. Under non-shear conditions and a triblock copolymer concentration suitable for direct-write printing, the composition is a viscoelastic solid (hydrogel) at a temperature of about 15&#xb0; C. to about 45&#xb0; C., and is a free-flowing liquid (sol) between 0&#xb0; C. and about 10&#xb0; C. The hydrogel form can be shear-thinned at about 15&#xb0; C. to about 45&#xb0; C. to form a sol suitable for a direct-write printer using an extruding print-head. The compositions covalently crosslink when flood-exposed to ultraviolet radiation. The compositions have utility in forming three-dimensional scaffolds for growing living cells.

Hydrogel compositions for direct-write printing applications

In one embodiment, an integrated circuit chip has an input/output (I/O) interface and programmable fabric. The I/O interface restricts access to scan testing of the chip by requiring (1) a specific scan-testing instruction, (2) a specific manufacturing key, and (3) a specific fabric pattern value from a specific set of registers in the programmed fabric. In addition or alternatively, the I/O interface has circuitry that enables scan testing of most of the logic of the I/O interface itself, including the logic being driven by the JTAG TAP state register.

Highly secure and extensive scan testing of integrated circuits

In one embodiment, a programmable logic device includes a memory and an input/output (I/O) interface adapted to enter a variable response mode responsive to an assertion of a control signal. The I/O interface is operable in the variable response mode to respond to a read command from an external device by retrieving data from the memory and to shift dummy data to the external device until an internal data ready signal is asserted.

Variable response mode for synchronous data read

A query processing method intersects two or more unsorted lists based on a conjunction of predicates. Each list comprises a union of multiple sorted segments. The method performs lazy segment merging and an adaptive n-ary intersecting process. The lazy segment merging comprises starting with each list being a union of completely unmerged segments, such that lookups into a given list involve separate lookups into each segment of the given list. The method intersects the lists according to the predicates while performing the lazy segment merging, such that the lazy segment merging reads in only those portions of each segment that are needed for the intersecting. As the intersecting proceeds and the lookups are performed, the intersecting selectively merges the segments together, based on a cost-benefit analysis of the cost of merging compared to the benefit produced by reducing a number of lookups.

Adaptive lazy merging

Various techniques are provided to flexibly update data fields stored in multi-bit registers. In one example, a method of updating a control register within an integrated circuit includes storing a plurality of initial bit values in the control register within the integrated circuit. The method also includes receiving a data set comprising one or more corrective bit values and one or more non-corrective bit values. The method also includes performing a logic operation on the received data set and the initial bit values to provide updated bit values. The method also includes replacing the initial bit values with the updated bit values in the control register.

Flexible updating of multi-bit registers

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Beaverton, OR, United States of America

Wei Han