Alibaba Group Holding Limited

South China University of Technology

Beijing Brace Damping Engineering Technology Co., Ltd

Chinese Academy of Sciences

Xiaomi Inc.

China Construction Fourth Engineering Division Corp. Ltd

Beijing Xiaomi Mobile Software Co., Ltd.

State Grid Corporation of China

Petrochina Company Limited

Chinese Academy of Medical Sciences

Alibaba (china) Co., Ltd.

China Electric Power Research Institute Company Limited

Beijing Brace Damper Technology Co., Ltd.

China Construcion Fourth Engineering Dmsion Green Building Technology (guangdong), Ltd

China Construction Fourth Engineering Division Green Building Technology (guangdong), Ltd

Wei Han

Junxian Zhao

Hongzhong Zheng

Dimin Niu

Yuhao Wang

Shuangchen Li

Lide Duan

Fei Sun

Fei Xue

Xiaoxin Fan

Hao Qin

Wei Wang

Gang Wang

Feng Zhang

Ming Liu

Hongguang Jin

Hui Hong

Zhaoxun Yuan

Qibin Liu

Jun Sui

Qiwu Huang

Xiangkun Yao

Zhi Luo

Guohui Yuan

Weijie Chen

Dan Li

Yin Zhu

Yuan Gao

Rui Yang

Kun Wu

Heng Liu

Chen Bo Li

Lixin Li

Tao Peng

Lin Cheng

Wei Xie

Wenjun Wang

Yan Nan Hu

Qinggang Zhou

Xiaowei Hu

Shiguang Li

Bin Qin

Yuanwei Fang

Chunsheng Liu

Yawen Zhang

Yun Zhou

Yuzhen Wan

Ying Qian

Zechen Wei

Shiqi Cui

Tianjiao Pu

Jun Yuan

Kezhu Jiang

Zhiqiu He

Yijun Yu

Qixiang Tian

Dehua Huang

Chenxi Wang

Xiaozhong Peng

Guiqiang Hao

Xilong Chen

Xuejing Chi

Shuangcheng Li

Boqin Qiang

Xiaona Shi

Dinglian Ban

Shixiong Fan

Ting Yu

Xingwei Liu

Xinjing Wu

Jiatong Du

Chunxia Che

Yulong Liang

Galian Gou

Kanghong Lu

Xilin Jing

Xiaoxin Chang

Xiaochuan Feng

Qiang Gui

Lifen Gu

Zhongdong Zhang

Duping Tan

Ruobing Chen

Haichao Yu

Yan Hu

A seismic resilient precast concrete frame structure includes precast solid columns, precast composite beams, T-shaped shear connectors having notches, and anti-buckling energy-dissipation connecting plates, wherein the precast composite beams are connected to the precast solid columns and each include a precast composite middle beam and precast composite cantilever beams arranged at two sides of each of the precast composite middle beams; tops of the precast composite cantilever beams and the precast composite middle beams are connected by the T-shaped shear connectors having notches, and the notches in the T-shaped shear connectors having notches are located at a neutral bending moment point of the frame structure under the action of a vertical load; and side surfaces of the precast composite cantilever beams and the precast composite middle beams are connected by means of the anti-buckling energy-dissipation connecting plates.

Seismic resilient precast concrete frame structure and construction method therefor

The building node includes an upper unit column, a lower unit column, an upper unit bottom beam, a lower unit ceiling beam, an upper connecting box, a lower connecting box, a connecting plate, an upper anchorage device, a lower anchorage device, an upper sleeve, a lower sleeve, a pull rod shear lock, position limiting nuts, and an injection pipe. The lower anchorage device is fixedly connected to the top plate of the lower connecting box; the lower position limiting nut is fixedly connected to the lower anchorage device; one end of the lower sleeve is fixedly connected to the lower anchorage device, and another end of the lower sleeve is fixedly connected to the top plate of the lower connecting box; the bottom of the upper sleeve is fixedly connected to the bottom plate of the upper connecting box.

High-rise modular steel structure building node in region of high seismic intensity and constructing method therefor

The present invention relates to a prefabricated infilled panel-frame structure capable of accommodating seismic-loading and seismic energy dissipation, and a construction method thereof, including a frame body, a prefabricated infilled panel group, a panel connector, and a disc spring assembly. During an earthquake, the present invention slides to dissipate energy only after the maximum starting sliding force is exceeded, thus providing the structure with a relatively high lateral stiffness prior to sliding. After an earthquake, the disc spring assembly of the present invention may provide a certain restoring force due to being compressed so as to reduce the residual displacement. Further, the present invention achieves the bidirectional deformation cooperation of the prefabricated infilled panel under earthquakes, so that the infilled panel may still achieve the function of seismic energy dissipation under the coupling action of in-plane and out-of-plane loads.

Prefabricated infilled panel-frame structure capable of accommodating seismic loading and seismic energy dissipation, and construction method

A friction energy dissipation column for bi-directional deformation cooperative and multi-stage working, includes two cantilever part I-shaped steel columns, a middle part I-shaped steel column, wherein the middle part I-shaped steel column is located between the two cantilever part I-shaped steel columns, and the middle part I-shaped steel column is detachably connected to the two cantilever part I-shaped steel columns via a pin shaft connector and a friction energy dissipation assembly. An upper end and a lower end web of the friction energy dissipation column are connected to the frame beam via a connecting plate, and the flanges on both sides are provided with haunched supports.

Friction energy dissipation column for bi-directional deformation cooperative and multi-stage working

The present invention relates to a variable friction energy dissipation prefabricated seismic-damping partition wall-frame structure and a construction method therefor. The variable friction energy dissipation prefabricated seismic-damping partition wall-frame structure includes a peripheral frame, prefabricated seismic-damping partition wall panels, rubber pads, a friction seismic-damping layer, horizontal force transfer members and a steel angle restraining members. The sliding friction of the partition wall can be significantly improved with increase of an inter-story drift, so that the partition wall has a larger hysteretic area and a higher energy dissipation capacity and can provide the structure with a relatively high additional damping ratio, so as to alleviate a seismic action. In addition, integral damage control of the partition wall can be better achieved, and the energy dissipation capacity of the partition wall under bidirectional seismic actions can be guaranteed.

Variable friction energy dissipation prefabricated seismic-damping partition wall-frame structure and construction method therefor

A resilient prestress-free steel structure includes the elastic centering beam and two pin-ended box column bases. The elastic centering beam includes two cantilever segment I-shaped steel beams, a middle segment I-shaped steel beam and buckling restrained high strength steel bars. The cantilever segment I-shaped steel beams are fixed to the two pin-ended box column bases, the middle segment I-shaped steel beam is connected between the two cantilever segment I-shaped steel beams, the buckling restrained high strength steel bars are symmetrically arranged. One end of each of the buckling restrained high strength steel bars is firmly connected with the web of each of the cantilever segment I-shaped steel beams, and the other end of each of the buckling restrained high strength steel bars is firmly connected with the web of the middle segment I-shaped steel beam. The resilient prestress-free steel structure is arranged in left and right symmetrical manner.

Resilient prestress-free steel structure formed by combining pin-ended columns with elastic centering beam

Various embodiments of the present disclosure relate to a computer-implemented method, a system, and a storage medium, where a graph stored in a computing system is logically divided into subgraphs, the subgraphs are stored on different interconnected (or coupled) devices in the computing system, and nodes of the subgraphs include hub nodes connected to adjacent subgraphs. Each device stores attributes and node structure information of the hub nodes of the subgraphs into other devices, and software or hardware prefetch engine on the device prefetches attributes and node structure information associated with a sampled node. A prefetcher on a device interfacing with the interconnected (or coupled) devices may further prefetch attributes and node structure information of nodes of the subgraphs on other devices. A traffic monitor is provided on an interface device to monitor traffic. When the traffic is small, the interface device prefetches node attributes and node structure information.

Computer-implemented method, system, and storage medium for prefetching in a distributed graph architecture

A system-in-package architecture in accordance with aspects includes a logic die and one or more memory dice coupled together in a three-dimensional slack. The logic die can include one or more global building blocks and a plurality of local building blocks. The number of local building blocks can be scalable. The local building blocks can include a plurality of engines and memory controllers. The memory controllers can be configured to directly couple one or more of the engines to the one or more memory dice. The number and type of local building blocks, and the number and types of engines and memory controllers can be scalable.

Scalable system-in-package architectures

Methods, apparatuses, and truncated multiplication circuitry for truncated multiplication are provided. Truncated multiplication circuitry includes a control register that includes a first section configured to store a first value representing truncating a most significant bit (MSB) of a partial product of a multiplier and a multiplicand, and a second section configured to store a value representing a truncation mode. The truncated multiplication circuitry also includes control circuitry configured to truncate the MSB of the partial product based on the truncation mode if the first section stores the first value. A method includes: in response to receiving a multiplier and a multiplicand, determining a partial product of the multiplier and the multiplicand; receiving a first value representing truncating a most significant bit (MSB) of the partial product and a value representing a truncation mode; and truncating the MSB of the partial product based on the truncation mode.

Low-power programmable truncated multiplication circuitry

A dual-model memory interface of a computing system is provided, configurable to present memory interfaces having differently-graded bandwidth capacity to different processors of the computing system. A mode switch controller of the memory interface controller, based on at least an arbitration rule written to a configuration register, switches the memory interface controller between a narrow-band mode and a wide-band mode. In each mode, the memory interface controller disables either a plurality of narrow-band memory interfaces of the memory interface controller according to a first bus standard, or a wide-band memory interface of the memory interface controller according to a second bus standard. The memory interface controller virtualizes a plurality of system memory units of the computing system as a virtual wide-band memory unit according to the second bus standard, or virtualizes a system memory unit of the computing system as a virtual narrow-band memory unit according to the first bus standard.

Dual-modal memory interface controller

The present disclosure relates to a method and an apparatus for approximating non-linear function. In some embodiments, an exemplary processing unit includes: one or more registers for storing a lookup table (LUT) and one or more operation elements communicatively coupled with the one or more registers. The LUT includes a control state and a plurality of data entries. The one or more operation elements are configured to: receive an input operand; select one or more bits from the input operand; select a data entry from the plurality of data entries using the one or more bits; and determine an approximation value of a non-linear activation function for the input operand using the data entry.

Apparatuses and methods for approximating nonlinear function

The present disclosure relates to an accelerator for systolic array-friendly data placement. The accelerator may include: a systolic array comprising a plurality of operation units, wherein the systolic array is configured to receive staged input data and perform operations using the staged input to generate staged output data, the staged output data comprising a number of segments; a controller configured to execute one or more instructions to generate a pattern generation signal; a data mask generator; and a memory configured to store the staged output data using the generated masks. The data mask generator may include circuitry configured to: receive the pattern generation signal from the controller, and, based on the received signal, generate a mask corresponding to each segment of the staged output data.

Systolic array-friendly data placement and control based on masked write

A chip or integrated circuit includes a layer that includes a first device and a second device. A scribe line is located between the first device and the second device and separates the first device from the second device. An electrically conductive connection traverses the scribe line and is coupled to the first device and the second device, thus connecting the first and second devices.

Using electrical connections that traverse scribe lines to connect devices on a chip

The systems and methods are configured to efficiently and effectively include processing capabilities in memory. In one embodiment, a processing in memory (PIM) chip a memory array, logic components, and an interconnection network. The memory array is configured to store information. In one exemplary implementation the memory array includes storage cells and array periphery components. The logic components can be configured to process information stored in the memory array. The interconnection network is configured to communicatively couple the logic components. The interconnection network can include interconnect wires, and a portion of the interconnect wires are located in a metal layer area that is located above the memory array.

Memory interconnection architecture systems and methods

The present disclosure relates to a system and a method for fabricating one or more integrated circuits (ICs). The system includes a plurality of logic tiles formed on a logic wafer and separated by at least one first scribe line, a respective logic tile including a function unit including circuitry configured to perform a respective function; at least one global interconnect configured to communicatively connect the plurality of logic tiles; a plurality of memory tiles formed on a memory wafer connected with the logic wafer, the plurality of memory tiles separated by at least one second scribe line that is substantially aligned with the at least one first scribe line, wherein the logic wafer and the memory wafer are diced along the at least one first scribe line and the at least one second scribe line to obtain a plurality of ICs, a respective IC including at least one logic tile connected with at least one memory tile.

Scalable and flexible architectures for integrated circuit (IC) design and fabrication

Growing community of inventors

Beijing, China

Wei Han