Altera Corporation

Wei-Guang Wu

Cheng-Hsiung Huang

Samit S Sengupta

Chih-Ching Shih

Yow-Juang Bill Liu

Hugh Sung-Ki O

Billy Jow-Tai Kwong

Yu-Cheng Richard Gao

In one aspect, the present invention comprises an electrostatic discharge (ESD) protection circuit comprising a plurality of input circuits in which each input circuit comprises a first PMOS and a first NMOS transistor connected in series between a power supply and ground and first and second inverters connected to the gates of the first PMOS and NMOS transistors. Each inverter connected to the gate of the first NMOS transistor comprises a second NMOS transistor connected between that gate and ground and the ratio of the width of the gate of the second NMOS transistor to the width of the gate of the first NMOS transistor of each of the input circuits is substantially the same. In another aspect of the invention, a multi-fingered gate transistor is formed in a first well of one conductivity type that is surrounded by a second well of the same conductivity type from which it is separated by a shallow trench isolation and a portion of the substrate. The second well is used as a tap for the first well with a significant increase in the resistance of the substrate current path. A process for forming this structure is a further aspect of the invention.

Electrostatic discharge (ESD) protection device for use with multiple I/O standards

The present invention provides an ESD device for protecting thin oxide layers in transistors or capacitors in an integrated circuit. In one embodiment, the ESD device includes a silicon-controlled rectifier (SCR), the SCR including a PNP bipolar transistor and a NPN bipolar transistor. The ESD device further includes first and second trigger devices coupled to the SCR and configured to simultaneously turn on the PNP bipolar transistor and the NPN bipolar transistor in response to an ESD pulse on the ESD device. The base of the NPN bipolar transistor is floating to allow a first external resistor to be connected between the base and emitter of the NPN bipolar transistor. A second external resistor can be connected between the base and emitter of the PNP bipolar transistor.

Fast trigger ESD device for protection of integrated circuits

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Sunnyvale, CA, United States of America

Wei-Guang Wu