Sharp Laboratories of America, Inc

Wei Gao

Yoshi Ono

Bruce Dale Ulrich

Sheng Teng Hsu

John F Conley, Jr

Tingkai Li

David R Evans

Fengyan Zhang

Wei-Wei Zhuang

Pooran Chandra Joshi

Keizo Sakiyama

Robert A Barrowcliff

Steven Roy Droes

Osamu Nishio

A grayscale mask made from semi-transparent film layers is provided, along with an associated fabrication method. The method provides a transparent substrate, such as quartz, with a surface. A first layer of a semi-transparent film having a surface with a first surface area, is formed overlying the substrate surface. At least a second layer of the semi-transparent film having a surface with a second surface area greater than the first surface area, is formed overlying the first layer. A first vertical region is formed having a light first attenuation parameter through the combination of substrate, first layer, and second layer. A second vertical region is formed having a light second attenuation parameter through the combination of the first layer and substrate, and a third vertical region is formed having a light third attenuation parameter through the substrate.

Semi-transparent film grayscale mask

An iridium oxide (IrOx) nanowire neural sensor array and associated fabrication method are provided. The method provides a substrate with a conductive layer overlying the substrate, and a dielectric layer overlying the conductive layer. The substrate can be a material such as Si, SiO, quartz, glass, or polyimide, and the conductive layer is a material such as ITO, SnO, ZnO, TiO, doped ITO, doped SnO, doped ZnO, doped TiO, TiN, TaN, Au, Pt, or Ir. The dielectric layer is selectively wet etched, forming contact holes with sloped walls in the dielectric layer and exposing regions of the conductive layer. IrOx nanowire neural interfaces are grown from the exposed regions of the conductive layer. The IrOx nanowire neural interfaces each have a cross-section in a range of 0.5 to 10 micrometers, and may be shaped as a circle, rectangle, or oval.

Method for forming an iridium oxide (IrOx) nanowire neural sensor array

A method is provided for forming an error diffusion-derived sub-resolutional grayscale reticle. The method forms at least one partial-light transmissive layer overlying a transparent substrate. At least one unit cell in formed in the transmissive layer. The unit cell is formed by selecting the number of reduced-transmission pixels in the unit cell, and forming a sub-pattern of reduced-transmission pixels in the unit cell. The unit cell is sub-resolutional at a first wavelength.

Error diffusion-derived sub-resolutional grayscale reticle

A sub-resolutional grayscale reticle and associated fabrication method have been presented. The method provides a transparent substrate, and forms a plurality of coincident partial-light transmissive layers overlying the transparent substrate. A pattern is formed, sub-resolutional at a first wavelength, in at least one of the transmissive layers. If there are n transmissive layers, the reticle transmits at least (n+1) intensities of light. In one aspect, each of the plurality of transmissive layers has the same extinction coefficient and the same thickness. In other aspects, the transmissive layers may have different thickness. Then, even if the extinction coefficients are the same, the attenuation of light through each layer is different. The transmission characteristics of the reticle can be further varied if the transmissive layers have different extinction coefficients. Likewise, the transmission characteristics through the sub-resolutional patterns can be varied.

Sub-resolutional grayscale reticle

A method of fabricating a grayscale mask includes preparing a silicon wafer; depositing a layer of SiNdirectly on the silicon wafer; implanting Hions into the silicon wafer to form a defect layer; depositing a first layer of SiONdirectly on the SiNlayer; depositing a layer of SRO directly on the first layer of SiON; patterning and etching the SRO layer to form a microlens array in the SRO layer; depositing a second layer of SiONon the SRO microlens array; CMP to planarize the second layer of SiON; bonding and cleaving the planarized SiONto a quartz plate to form a graymask reticle; etching to remove silicon from the bonded structure; etching to remove SiONand SiNfrom the bonded structure; and cleaning and drying the graymask reticle.

Method of fabricating grayscale mask using smart cut&#xae; wafer bonding process

A method of fabricating an electroluminescent device includes, on a prepared substrate, depositing a rare earth-doped silicon-rich layer on gate oxide layer as a light emitting layer; and annealing and oxidizing the structure to repair any damage caused to the rare earth-doped silicon-rich layer; and incorporating the electroluminescent device into a CMOS IC. An electroluminescent device fabricated according to the method of the invention includes a substrate, a rare earth-doped silicon-rich layer formed on the gate oxide layer for emitting a light of a pre-determined wavelength; a top electrode formed on the rare earth-doped silicon-rich layer; and associated CMOS IC structures fabricated thereabout.

Terbium-doped, silicon-rich oxide electroluminescent devices and method of making the same

A method of fabricating a grayscale mask includes preparing a quartz wafer; depositing a layer of SiNon the quartz wafer; depositing a layer of titanium/TEOS directly on the SiNlayer on the backside of the quartz wafer; removing the layer of SiNfrom the front side of the quartz wafer; depositing a layer of SRO directly on the front side of the quartz wafer; patterning a microlens array on the SRO layer; etching the SRO layer to form a microlens array in the SRO layer; depositing a layer of titanium; patterning and etching the titanium layer; depositing a layer of SiONon the SRO microlens array; CMP to planarize the layer of SiONremoving the titanium/TEOS layer from the backside of the quartz wafer; bonding the planarized SiONto a quartz reticle plate; and etching to remove SiNfrom the bonded structure to form a grayscale mask reticle.

Method of fabricating a grayscale mask using a wafer bonding process

A method of fabricating a grayscale reticle includes preparing a quartz wafer substrate; depositing a layer of SRO on the top surface of the quartz substrate; patterning and etching the SRO to form an initial microlens pattern using step-over lithography; patterning and etching the SRO to form a recessed pattern in the SRO; depositing an opaque film on the SRO; patterning and etching the opaque film; depositing and planarizing a planarizing layer; cutting the quartz wafer into rectangular pieces sized to be smaller than a selected blank reticle; bonding the a piece a to selected reticle blank to form a grayscale reticle; and using the grayscale reticle to form a microlens array on a photoimager.

Method of making a grayscale reticle using step-over lithography for shaping microlenses

A device and a fabrication method are provided for an EL device with a nanotip-contoured phosphor layer. The method comprises: forming a bottom electrode with nanotips; forming a phosphor layer overlying the bottom electrode, having irregularly-shaped top and bottom surfaces; and, forming a top electrode overlying the phosphor layer. The bottom electrode top surface has a nanotip contour, and the phosphor layer irregularly-shaped top and bottom surfaces have contours approximately matching the bottom electrode top surface nanotip contour. In one aspect, a contoured bottom dielectric is interposed between the bottom electrode and the phosphor layer, having top and bottoms surfaces with contours approximately matching the nanotip contour. Likewise, a top dielectric may be interposed between the top electrode and the phosphor layer, having a bottom surface with a contour approximately matching the contour of phosphor layer top surface.

Nanotip electrode electroluminescence device with contoured phosphor layer

A method, and corresponding transistor structure are provided for protecting the gate electrode from an underlying gate insulator. The method comprises: forming a gate insulator overlying a channel region; forming a first metal barrier overlying the gate insulator, having a thickness of less than 5 nanometers (nm); forming a second metal gate electrode overlying the first metal barrier, having a thickness of greater than 10 nm; and, establishing a gate electrode work function exclusively responsive to the second metal. The second metal gate electrode can be one of the following materials: elementary metals such as p+ poly, n+ poly. Ta, W, Re, RuO2, Pt, Ti, Hf, Zr, Cu, V, Ir, Ni, Mn, Co, NbO, Pd, Mo, TaSiN, and Nb, and binary metals such as WN, TaN, and TiN. The first metal barrier can be a binary metal, such as TaN, TiN, or WN.

Reactive gate electrode conductive barrier

MOSFET gate structures are provided comprising a niobium monoxide gate, overlying a gate dielectric. The niobium monoxide gate may have a low work function suitable for use as an NMOS gate.

Conductive niobium oxide gate MOSFET

A method is provided for forming a rare earth (RE) element-doped silicon (Si) oxide film with nanocrystalline (nc) Si particles. The method comprises: providing a first target of Si, embedded with a first rare earth element; providing a second target of Si; co-sputtering the first and second targets; forming a Si-rich Si oxide (SRSO) film on a substrate, doped with the first rare earth element; and, annealing the rare earth element-doped SRSO film. The first target is doped with a rare earth element such as erbium (Er), ytterbium (Yb), cerium (Ce), praseodymium (Pr), or terbium (Tb). The sputtering power is in the range of about 75 to 300 watts (W). Different sputtering powers are applied to the two targets. Also, deposition can be controlled by varying the effective areas of the two targets. For example, one of the targets can be partially covered.

Sputter-deposited rare earth element-doped silicon oxide film with silicon nanocrystals for electroluminescence applications

A method for forming a high-luminescence Si electroluminescence (EL) phosphor is provided, with an EL device made from the Si phosphor. The method comprises: depositing a silicon-rich oxide (SRO) film, with Si nanocrystals, having a refractive index in the range of 1.5 to 2.1, and a porosity in the range of 5 to 20%; and, post-annealing the SRO film in an oxygen atmosphere. DC-sputtering or PECVD processes can be used to deposit the SRO film. In one aspect the method further comprises: HF buffered oxide etching (BOE) the SRO film; and, re-oxidizing the SRO film, to form a SiOlayer around the Si nanocrystals in the SRO film. In one aspect, the SRO film is re-oxidized by annealing in an oxygen atmosphere. In this manner, a layer of SiOis formed around the Si nanocrystals having a thickness in the range of 1 to 5 nanometers (nm).

Method of forming high-luminescence silicon electroluminescence device

Provided are an electroluminescence (EL) device and corresponding method for forming a rare earth element-doped silicon (Si)/Si dioxide (SiO2) lattice structure. The method comprises: providing a substrate; DC sputtering a layer of amorphous Si overlying the substrate; DC sputtering a rare earth element; in response, doping the Si layer with the rare earth element; DC sputtering a layer of SiO2 overlying the rare earth-doped Si; forming a lattice structure; annealing; and, in response to the annealing, forming nanocrystals in the rare-earth doped Si having a grain size in the range of 1 to 5 nanometers (nm). In one aspect, the rare earth element and Si are co-DC sputtered. Typically, the steps of DC sputtering Si, DC sputtering the rare earth element, and DC sputtering the SiO2 are repeated 5 to 60 cycles, so that the lattice structure includes the plurality (5-60) of alternating SiO2 and rare earth element-doped Si layers.

Rare earth element-doped silicon/silicon dioxide lattice structure

A method is provided for forming an electroluminescent device. The method comprises: providing a type IV semiconductor material substrate; forming a p+/n+ junction in the substrate, typically a plurality of interleaved p+/n+ junctions are formed; and, forming an electroluminescent layer overlying the p+/n+ junction(s) in the substrate. The type IV semiconductor material substrate can be Si, C, Ge, SiGe, or SiC. For example, the substrate can be Si on insulator (SOI), bulk Si, Si on glass, or Si on plastic. The electroluminescent layer can be a material such as nanocrystalline Si, nanocrystalline Ge, fluorescent polymers, or type II&#x2013;VI materials such as ZnO, ZnS, ZnSe, CdSe, and CdS. In some aspect, the method further comprises forming an insulator film interposed between the substrate and the electroluminescent layer. In another aspect, the method comprises forming a conductive electrode overlying the electroluminescent layer.

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Vancouver, WA, United States of America

Wei Gao