Winbond Electronics Corporation

Leap Semiconductor Corp.

Other

Windbond Electronics Corp.

Piecemakers Technology, Inc.

Wei-Fan Chen

Shi-Tron Lin

Kuo-Chi Tsai

Ta-Lee Yu

Chenhsin Lien

Fu-Chien Chiu

Chen-Hsin Lien

Chun-Mai Liu

Chuan-Jane Chao

Ming-Lun Chang

Shu-Chuan Lee

Chien-Ti Hou

Chun-Peng Wu

Kung-Yen Su

Chih-Yao Huang

Wen-Shiang Liao

Wan-Yun Lin

A temperature sensing device includes a resistor string and a control circuitry. The resistor string includes a variable resistor, a first resistor, and a second resistor which are coupled in series with each other. The resistor string is coupled between a sensing end and a reference ground voltage. The first resistor and the second resistor are coupled to a monitoring end to provide a monitoring voltage. The control circuitry compares the monitoring voltage with a plurality of reference voltages to generate sensing temperature information, and generate adjustment information according to the sensing temperature information. The control circuitry adjusts a resistance provided by the variable resistor according to the adjustment information. The first resistor is a polysilicon resistor, and the second resistor is a silicon carbide diffusion resistor.

Temperature sensing device

A method of manufacturing a silicon carbide semiconductor power device is provided. In the method, the power device in high voltage (HV) region and CMOS device in the low voltage (LV) region are formed together, so the cost and time can be saved efficiently. First, a first drift layer is formed on a substrate, and then a shielding region is formed in the first drift layer. The shielding region includes a continuous region in the LV region. Then, a second drift layer is formed on the first drift layer. A pick-up region is formed in the second drift layer, wherein the pick-up region connects to the continuous region of the shielding region, and then NMOS and PMOS in the LV region and the power device in HV region are formed simultaneously. NMOS and PMOS are surrounded by the pick-up region and the continuous region, thereby minimizing body effect.

Method of manufacturing silicon carbide semiconductor power device

A semiconductor power device includes a substrate, a drift layer disposed on the substrate, buried doped regions, gates, a gate insulation layer, well regions, source regions, and well contact regions. The buried doped regions are in the drift layer and parallel to each other, and each of the buried doped regions is a predetermined distance from an upper surface of the drift layer. The gates are on the drift layer and directly above the buried doped regions. The gate insulation layer is between the drift layer and the gates. The well regions are in the drift layer between the gates and separated from the buried doped regions, wherein the well regions and the buried doped regions are electrically connected. The source regions are within the well regions between the gates, and each of the well contact regions passes through the source region and contacts with the well.

Semiconductor power device and method of manufacturing the same

A driving voltage generating device includes a temperature detector, a controlling circuitry, a voltage generator, and an output stage circuitry. The temperature detector is coupled to a control terminal of a power transistor and is configured to generate temperature detection information by detecting an ambient temperature. The controlling circuitry is coupled to the temperature detector and generates an activation signal by determining whether the ambient temperature is abnormal according to the temperature detection information. The voltage generator generates an operation power according to the activation signal. The output stage circuitry is coupled to the voltage generator, generates a driving voltage according to the operation power, and provides the driving voltage to the control terminal of the power transistor.

Driving voltage generating device

A merged PiN Schottky (MPS) diode includes a substrate, a first epitaxial layer of a first conductivity type, doped regions of a second conductivity type, a second epitaxial layer of the first conductivity type, and a Schottky metal layer. The first epitaxial layer is disposed on the first surface of the substrate. The doped regions are disposed in a surface of the first epitaxial layer, wherein the doped regions consist of first portions and second portions, the first portions are electrically floating, and the second portions are electrically connected to a top metal. The second epitaxial layer is disposed on the surface of the first epitaxial layer, wherein trenches are formed in the second epitaxial layer to expose the second portions of the doped regions. The Schottky metal layer is conformally deposited on the second epitaxial layer and the exposed second portions of the doped regions.

Method of manufacturing merged PiN Schottky (MPS) diode

A silicon carbide semiconductor power transistor and a method of manufacturing the same. The silicon carbide semiconductor power transistor of the disclosure includes a substrate made of silicon carbide (SiC), a drift layer disposed on the substrate, a gate layer formed on the drift layer, a plurality of first and second well pick-up regions disposed in the drift layer, a plurality of source electrodes, and a plurality of contacts. A plurality of V-grooves is formed in the drift layer. A first opening is formed in the gate layer at a bottom of each of the V-grooves, and a second opening is formed in the gate layer at a top of the drift layer between the V-grooves. The plurality of contacts is disposed inside the second opening to be in direct contact with the second well pick-up regions.

Silicon carbide semiconductor power transistor and method of manufacturing the same

A wide-band gap semiconductor device and a method of manufacturing the same are provided. The wide-band gap semiconductor device of the disclosure includes a substrate, an epitaxial layer, an array of merged PN junction Schottky (MPS) diode, and an edge termination area surrounding the array of MPS diode. The epitaxial layer includes a first plane, a second plane, and trenches between the first plane and the second plane. The array of MPS diode is formed in the first plane of the epitaxial layer. The edge termination area includes a floating ring region having floating rings formed in the second plane of the epitaxial layer, and a transition region between the floating ring region and the array of MPS diode. The transition region includes a PIN diode formed in the plurality of trenches and on the epitaxial layer between the trenches.

Method of manufacturing wide-band gap semiconductor device

An electronic device and a temperature detection device thereof are provided. The temperature detection device includes a differential stage circuit and an output stage circuit. The differential stage circuit includes a first differential end and a second differential end, and includes a cross-coupled transistor element, a first resistor and a second transistor. The cross-coupled transistor element receives a first voltage. The first resistor is coupled between the first differential end and a second voltage, and the first resistor is poly-silicon resistor. The second resistor is coupled between the second differential end and the second voltage, and the second resistor is a silicon carbide diffusion resistor. The output stage circuit generates a driving voltage according to a first control voltage on the first differential end and a second control voltage on the second differential end.

Electronic device and temperature detection device thereof

A short-circuit protection circuitry is adapted for a power transistor. The short-circuit protection circuitry includes a first diode, a first resistor, a voltage dividing circuit, a gate voltage generator, a pull-down circuit, and a control signal generator. The first diode is coupled to a drain of the power transistor. The first resistor is coupled between the first diode and the power transistor. The voltage dividing circuit is coupled between a gate and a source of the power transistor to generate a dividing voltage. The gate voltage generator provides a gate voltage to the gate of the power transistor according to a first driving signal and a second driving signal. The pull-down circuit pulls down the gate voltage according to a control signal. The control signal generator generates the control signal according to the first driving signal, a voltage on the anode of the first diode and the dividing voltage.

Short-circuit protection circuitry

Merged PiN Schottky (MPS) diode and method of manufacturing the same

Wide-band gap semiconductor device and method of manufacturing the same

An one-time programmable memory cell includes: an upper electrode; an insulating layer beneath the upper electrode; and a lower electrode with electrical field enhancement structure beneath the insulating layer, wherein the electrical field enhancement structure has a least one tip portion. The one-time programmable memory cell also includes a shallow trench isolation region, disposed adjacent to the insulating layer and the lower electrode, wherein the electrical field enhancement structure is surrounded by the shallow trench isolation region and the upper electrode partially covers the shallow trench isolation region.

Anti-fuse one-time programmable memory cell and related array structure

A protection circuit protects an integrated circuit ('IC') from peak voltages and includes a voltage divider coupled to a silicon controlled rectifier. The voltage divider allows for adjustment of the trigger voltage, trigger current, and holding voltage of the protection circuit so that the protection circuit can conduct current after a particular voltage level has been applied to the protection circuit without accidental triggering on by, for example, noise.

Protection circuit for electrostatic discharge

The present invention provides a combinded FOX and poly gate structure, for effectively reducing the trigger voltage of a conventional field device, for improving the robustness of a NMOS transistor of a small drive I/O circuit, and for improving the ESD performance of a stack-gate voltage tolerant I/O.

Electrostatic discharge (ESD) protection device

An electrostatic discharge protection device formed on a substrate. The electrostatic discharge protection device includes a first isolation region formed over the substrate, an active region formed over the substrate and enclosed by the first isolation region, a second isolation region formed on the substrate and substantially surrounded by the active region, a first gate element formed in the active region, the first gate element having a first end extending over the first isolation region and a second end extending over the second isolation region, a drain region formed in the active region at a first side of the first gate element, a source region formed in the active region at a second side of the first gate element, a drain contact for electrically coupling the drain region to a first node, and a source contact for electrically coupling the source region to a second node.

Growing community of inventors

Taichung, Taiwan

Wei-Fan Chen