Taiwan Semiconductor Manufacturing Comp. Ltd.

Richtek Technology Corporation

Tsinghua University

Wistron Neweb Corporation

Wei-Chung Chang

Hung-Jui Kuo

Ming-Che Ho

Nien-Hui Kung

Yu-Jen Cheng

Shang-Ching Tseng

Chieh-Min Lo

Hsing-Yu Tuan

Chih-Wei Mu

Kuan-Wei Tseng

Sheng-Tsung Chen

An antenna structure includes a metal mechanism element, a ground element, a feeding radiation element, a first radiation element, a second radiation element, a parasitic radiation element, a tuning circuit, and a nonconductive support element. The metal mechanism element has a slot. The metal mechanism element includes a first grounding portion and a second grounding portion. The slot is positioned between the first grounding portion and the second grounding portion. The feeding radiation element has a feeding point. The first radiation element is coupled to the feeding radiation element. The second radiation element is coupled to the feeding radiation element. The parasitic radiation element is coupled to the ground element. The parasitic radiation element is adjacent to the first radiation element and the second radiation element. The tuning circuit is coupled between the first grounding portion and the second grounding portion of the metal mechanism element.

Antenna structure

Semiconductor package includes substrate, first barrier layer, second barrier layer, routing via, first routing pattern, second routing pattern, semiconductor die. Substrate has through hole with tapered profile, wider at frontside surface than at backside surface of substrate. First barrier layer extends on backside surface. Second barrier layer extends along sidewalls of through hole and on frontside surface. Routing via fills through hole and is separated from sidewalls of through hole by at least second barrier layer. First routing pattern extends over first barrier layer on backside surface and over routing via. First routing pattern is electrically connected to end of routing via and has protrusion protruding towards end of routing via in correspondence of through hole. Second routing pattern extends over second barrier layer on frontside surface. Second routing pattern directly contacts another end of routing via. Semiconductor die is electrically connected to routing via by first routing pattern.

Semiconductor package

Semiconductor package and manufacturing method thereof

A semiconductor package includes a substrate, a composite seed-barrier layer, a routing via, and a semiconductor die. The substrate has a through hole formed therethrough. The composite seed-barrier layer extends on sidewalls of the through hole and includes a first barrier layer, a seed layer, and a second barrier layer sequentially stacked on the sidewalls of the through hole. The routing via fills the through hole and is separated from the substrate by the composite seed-barrier layer. The semiconductor die is electrically connected to the routing via. Along the sidewalls of the through holes, at a level height corresponding to half of a total thickness of the substrate, the seed layer is present as inclusions of seed material surrounded by barrier material of the first barrier layer and the second barrier layer.

An interface control circuit complying with an interface specification includes: an interface signal transceiver circuit and a protection circuit. The interface signal transceiver circuit is coupled to a first interface connection pin and a second interface connection pin of a first interface connector circuit. The interface signal transceiver circuit is for transmitting and/or receiving an interface signal according to the interface specification. When the interface signal transceiver circuit operates under a first state, the protection circuit determines whether a foreign object exists between the first interface connection pin and the second interface connection pin according to a voltage change or a current change at the second interface connection pin. Under the first state, the interface signal transceiver circuit generates a pull-up signal and a pull-down signal which are toggled with each other at the first interface connection pin.

Interface control circuit and control method thereof

Halogen-doped phosphorous nanoparticles and a manufacturing method thereof are provided. The manufacturing method includes a mixing process and a centrifugation or filtration process. The mixing process has the step of mixing a precursor with a reducing agent solution to form a mixed solution, the precursor is a halogen-based phosphide. Then, the mixed solution is centrifuged or filtrated to obtain the halogen-doped phosphorous nanoparticles.

Halogen doped phosphorus nanoparticles and manufacturing method thereof

The present invention discloses a method for controlling a voltage regulator, including steps of: converting an input voltage to an output voltage and providing an output current; sensing the output current; reducing the output voltage; and when the reduction of the output voltage causes the output current to change, setting the output voltage back to a value which does not change the output current.

Growing community of inventors

Hsinchu, Taiwan

Wei-Chung Chang