Realtek Semiconductor Inc.

Wei-Chou Wang

Shih-Hsiung Huang

Jian-Ru Lin

Chao-Cheng Lee

Yu-Chang Chen

Chen-Chih Huang

Ming-Cheng Chiang

Chih-Chien Chang

Chun-Hsiung Chang

Hsiang-An Yang

Shun-Ta Wu

Sheng-Huang Tsao

Tung-Hung Sung

A transmitter, a receiver and a transceiver are provided. The transceiver includes a hybrid transceiving circuit and a common-mode voltage control circuit. The hybrid transceiving circuit includes a digital-to-analog converter (DAC) circuit, a line driver coupled to the DAC circuit, a filtering and/or amplifying circuit coupled to the line driver, and an analog-to-digital converter (ADC) circuit coupled to the filtering and/or amplifying circuit. The common-mode voltage control circuit is electrically connected to a node of the hybrid transceiving circuit and is configured to detect a common-mode voltage of the node and to adjust the common-mode voltage of the node.

Transmitter, receiver and transceiver

Disclosed is a sample and hold circuit and method capable of amplifying an input signal. The method includes: in a sample phase, receiving a first (second) input signal with top electrodes of first (second) capacitors, and receiving the second (first) input signal with all bottom electrode(s) of at least a part of the first (second) capacitors; in a hold phase, stopping receiving the first (second) input signal with the top electrodes of the first (second) capacitors, and receiving a first (second) group of reference signals with the bottom electrodes of the first (second) capacitors, so that the first (second) capacitors provide a first (second) sample voltage on the top electrodes of the multiple first (second) capacitors through charge redistribution, wherein the first and second input signals are a pair of differential signals and they are opposite to each other.

Sample and hold circuit and method

A multi-stage switched capacitor circuit and an operation method thereof are provided. The multi-stage switched capacitor circuit includes a first operational stage, a second operational stage and a third operational stage that are serially connected in order. Each operational stage operates in a sample phase or a hold phase and generates a detection signal indicating an end of the hold phase. The operation method of the multi-stage switched capacitor circuit includes: controlling the second operational stage to operate in the hold phase when the detection signal of the first operational stage indicates the end of the hold phase of the first operational stage, and the detection signal of the third operational stage indicates the end of the hold phase of the third operational stage.

Multi-stage switched capacitor circuit and operation method thereof

A digital-to-analog converter (DAC) device includes a DAC circuitry. The DAC circuitry includes a first DAC circuit and a second DAC circuit. The first DAC circuit is configured to generate a first signal according to a plurality of least significant bits of an input signal. The second DAC circuit is configured to output a second signal according to a plurality of most significant bits of the input signal. A first turn-on time of at least one current source circuit in the first DAC circuit is configured to set the first signal.

Digital to analog converter device and current control method

A soft-start circuit and a method thereof are described. The circuit includes an amplifier and a voltage ramp generator. The amplifier has a first input end, a second input end, an output end, and a power source control end. The first input end is coupled to a reference voltage. The second input end is coupled to a feedback voltage. The output end outputs an output voltage, and the feedback voltage corresponds to the output voltage. The voltage ramp generator is coupled to the power source control end, and generates a ramp-up voltage. When the ramp-up voltage is lower than a threshold value, the output voltage rises with the ramp-up voltage. When the ramp-up voltage is not lower than the threshold voltage, the output voltage remains at a stable value. A surge current occurring during smooth soft-start or even in operation is thus prevented.

Soft-start circuit having a ramp-up voltage and method thereof

A signal generating apparatus comprises an amplifier, which comprises differential input terminals for receiving a first input signal, a common mode output signal adjusting terminal for receiving a second input signal, and an output terminal. The signal generating apparatus may provide two or more differential output signals according to the first input signal, and provide two or more common mode output signals according to the second input signal. The amplifier provides an output signal comprising one of the differential output signals and one of the common mode output signals at the output terminal.

Signal generating apparatus and method thereof

A soft-start device including a current source, a first transistor, and a second transistor is described. The first transistor is coupled to the current source, and an amount of current conducted by the first transistor is determined according to a voltage. The second transistor is also coupled to the current source, and an amount of current conducted by the second transistor is determined according to a fixed bias. An initial voltage value of the voltage is smaller than a voltage value of the fixed bias. However, after a soft start, the voltage value of the first voltage is increased gradually to be larger than the voltage value of the fixed bias, such that the soft start may be implemented smoothly.

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Hsinchu, Taiwan

Wei-Chou Wang