Taiwan Semiconductor Manufacturing Comp. Ltd.

Epistar Corporation

Huga Optotech Inc.

High Power Opto, Inc.

Wei-Chih Wen

Chung-Te Lin

Han-Ting Tsai

Chien-Min Lee

Tai-Yen Peng

Hui-Hsien Wei

Pin-Ren Dai

Sheng-Chih Lai

Chun-Hsiang Tu

Yen-Tai Chao

Sen-Jung Hsu

Tao-Chi Chang

Ou Chen

Jyu-Horng Shieh

Yu-Shou Wang

Jing-Feng Huang

Yu-Teng Dai

Tai-Chun Wang

Yu-Ming Lin

Yen-Ming Chen

Hai-Ching Chen

Han-Jong Chia

Dian-Hau Chen

Yu-Wei Jiang

Chih-Sung Chang

Kai-Wen Cheng

Shiou-Yi Kuo

Tsung-Chieh Hsiao

Liang-Wei Wang

Po-Ting Lin

Wu-Wei Tsai

Po-Sheng Lu

Yu-Jen Wang

Liang-Jyi Yan

Kuo-Chen Wu

Jun-Sheng Li

Chih-Ping Hsu

Yu-Ming Hsiang

Yan-Yi Chen

Der-Wei Tu

Po-Hung Lai

A method of forming a semiconductor memory device includes: forming a stack structure on a substrate, the stack structure including a plurality of dielectric layers and a plurality of sacrificial layers alternatingly stacked in a Z direction substantially perpendicular to the substrate; forming a plurality of source/drain trenches in the stack structure; conformally forming a barrier layer in the source/drain trenches, and then filling the source/drain trenches with a plurality of sacrificial segments; forming a protection layer over the stack structure to cover the barrier layer and the sacrificial segments; removing the sacrificial layers of the stack structure to form a plurality of spaces among the dielectric layers; forming a plurality of conductive layers in the spaces; sequentially removing the protection layer, the sacrificial segments and the barrier layer; and forming a plurality of memory structures in the source/drain trenches.

Method of forming semiconductor memory device

A memory device and a manufacturing method thereof is described. The memory device includes a transistor structure over a substrate and a ferroelectric capacitor structure electrically connected with the transistor structure. The ferroelectric capacitor structure includes a top electrode layer, a bottom electrode layer and a ferroelectric stack sandwiched there-between. The ferroelectric stack includes a first ferroelectric layer, a first stabilizing layer, and one of a second ferroelectric layer or a second stabilizing layer. Materials of the first stabilizing layer and a second stabilizing layer include a metal oxide material.

Semiconductor device and manufacturing method thereof

A memory device includes a bottom electrode contact, a magnetic tunnel junction pattern, a protection insulating layer, a first capping layer, an interlayer insulating layer, and a second capping layer. The magnetic tunnel junction pattern is over the bottom electrode contact. The protection insulating layer surrounds the magnetic tunnel junction pattern. The first capping layer surrounds the protection insulating layer. The interlayer insulating layer surrounds the first capping layer. The second capping layer is over the first capping layer and the interlayer insulating layer.

Integrated circuit device

In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode.

Magnetic random access memory and manufacturing method thereof

An IC structure comprises a substrate, a first dielectric structure, a second dielectric structure, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first dielectric structure is over the memory region. The second dielectric structure laterally extends from the first dielectric structure to over the logic region. The second dielectric structure has a thickness less than a thickness of the first dielectric structure. The first via structure extends through the first dielectric structure. A top segment of the first via structure is higher than a top surface of the first dielectric structure. The first memory cell structure is over the first via structure.

Integrated circuit structure

A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.

Semiconductor device including vertical routing structure and method for manufacturing the same

A light-emitting device includes: a substrate having a top surface, wherein the top surface comprises a first portion and a second portion; a first semiconductor stack on the first portion, comprising a first upper surface and a first side wall; and a second semiconductor stack on the first upper surface, comprising a second upper surface and a second side wall, and wherein the second side wall connects the first upper surface; wherein the first semiconductor stack comprises a dislocation stop layer; wherein the dislocation stop layer comprises AlGaN; and wherein the first side wall and the second portion of the top surface form an acute angle α between thereof.

Light-emitting device and manufacturing method thereof

A device includes a resistance switching layer, a capping layer, a top electrode, a first spacer, and a second spacer. The resistance switching layer is over a substrate. The capping layer is over the resistance switching layer. The top electrode is over the capping layer. The first spacer lines the resistance switching layer and the capping layer. The second spacer lines the first spacer. The capping layer is in contact with the top electrode, the first spacer, and the second spacer.

Semiconductor device

A semiconductor device includes a bottom electrode; a magnetic tunneling junction (MTJ) element over the bottom electrode; a top electrode over the MTJ element; and a sidewall spacer abutting the MTJ element, wherein at least one of the bottom electrode, the top electrode, and the sidewall spacer includes a magnetic material.

Structure and method for MRAM devices

A device includes a conductive feature, a dielectric layer, a bottom electrode via, and a liner layer. The dielectric layer is over the conductive feature. The bottom electrode via is in the dielectric layer and over the conductive feature. A topmost surface of the bottom electrode via is substantially flat. A liner layer cups an underside of the bottom electrode via. The liner layer has a topmost end substantially level with the topmost surface of the bottom electrode via.

An IC structure comprises a substrate, a first material layer, a second material layer, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first material layer is disposed on the memory region and the logic region. The second material layer is disposed on the first material layer only at the memory region. The first via structure formed in the first material layer and the second material layer. The memory cell structure is over the first via structure.

A light-emitting device includes a substrate having a top surface, wherein the top surface includes a first portion and a second portion; a first semiconductor stack on the first portion, including a first upper surface and a first side wall; and a second semiconductor stack on the first upper surface, including a second upper surface and a second side wall, and wherein the second side wall connects the first upper surface; wherein the first semiconductor stack includes a dislocation stop layer; and wherein the first side wall and the second portion of the top surface form an acute angle &#x3b1; between thereof.

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Hsinchu, Taiwan

Wei-Chih Wen