Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

Wei-Chih Hou

Jiun-Yun Li

Yen Chuang

Yu-Jui Wu

Chia-Yu Liu

Nai-Wen Hsu

Pao-Chuan Shih

Pao-chuan Shih

The current disclosure describes a new vertical tunnel field-effect transistor (TFET). The TFET includes a source layer over a substrate. A first channel layer is formed over the source layer. A drain layer is stacked over the first channel layer with a second channel layer stacked therebetween. The drain layer and the second channel layer overlap a first surface portion of the first channel layer. A gate structure is positioned over the channel layer by a second surface portion of the channel layer and contacts a sidewall of the second channel layer.

Vertical tunnel field-effect transistor with u-shaped gate and band aligner

A flash memory device includes a substrate, a semiconductor quantum well layer, a semiconductor spacer, a semiconductor channel layer, a gate structure, and source/drain regions. The semiconductor quantum well layer is formed of a first semiconductor material and is disposed over the substrate. The semiconductor spacer is formed of a second semiconductor material and is disposed over the first semiconductor channel layer. The semiconductor channel layer is formed of the first semiconductor material and is disposed over the semiconductor spacer. Thea gate structure is over the second semiconductor channel layer. The source/drain regions are over the substrate and are on opposite sides of the gate structure.

Flash memory device and method thereof

Vertical tunnel field-effect transistor with U-shaped gate and band aligner

Growing community of inventors

Taichung, Taiwan

Wei-Chih Hou