Chroma Ate Inc.

Quanta Computer Incorporated

Seriphy Technology Corporation

Wei-Chih Chen

Yi-Yen Lin

Shang-Pin Chen

Pin-Hao Hung

Ben-Mou Yu

Chun-Wei Chang

Yangtzu Lee

Shen-Hao Tsai

Tzu-wei Chiu

Che-yen Huang

The present application discloses a semiconductor structure. The semiconductor structure a top die and a bottom die, and the maximum die size is constrained to reticle dimension. Each die includes (1) core: computation circuits, (2) phy: analog circuit connecting to memory, (3) I/O: analog circuit connecting output elements, (4) SERDES: serial high speed analog circuit, (5) intra-stack connection circuit, and (6) cache memory. This semiconductor structure can be chapleted design for high wafer yield with least tape out masks for cost saving. The intra-stack connection circuit connects the top die and the bottom die in the shortest distance (about tens of micrometers), so as to provide high signal quality and power efficiency.

Semiconductor structure and semiconductor device

A wafer inspection system includes a carrier device, a probe card, a first metal kit and a surround separating unit. The probe card includes a detection portion and a conductive layer surrounding the detection portion and disposed on its bottom surface. The first metal kit is configured at a bottom portion of the probe card and coupled to the conductive layer and includes a first window for the detection portion to extend out and a first ring piece extending from a periphery of the first window. The surround separating unit includes a conductive wraparound body surrounding and laterally enclosing the detection portion and a wafer to be inspected during probing. The probe card, first metal kit, carrier device, and conductive wraparound body jointly define an space range, shielding the detection portion and wafer from external noise or interference sources, thereby improving inspection accuracy.

Wafer inspection system

A voltage sensor system for determining an abnormal circuit condition in a multi-layer printed circuit board is disclosed. The printed circuit board has a plurality of layers. One of the layers includes a trace network and a sensor circuit. The sensor circuit includes the trace network and a sensing point. The sensor circuit is coupled between a voltage supply and a ground. A controller is coupled to the sensing point. The controller is operable to determine a voltage of the sensing point and compare the voltage to a threshold value to determine an abnormal circuit condition in the printed circuit board.

Trace level voltage sensor for multi-layer printed circuit boards

A wafer inspection system and a wafer inspection equipment thereof are provided. The wafer inspection system includes a susceptor device, probe card, and bridge module. The susceptor device includes a susceptor unit for placing a wafer under test. The probe card includes a probing portion and conducting portion. The conducting portion is disposed at the periphery of the probing portion and has a contact surface. The bridge module includes transmission units extended upward, positioned adjacent to a wafer placement area, and coupled to the susceptor unit. When the probing portion comes into contact with a testing point of the wafer, the contact surface of the conducting portion gets coupled to the transmission units to transmit a test signal to the probe card via the transmission units and conducting portion and thus form a test loop. Thus, the test loop path can be shortened and the accuracy of signal transmission and inspection can be enhanced.

Wafer inspection system and wafer inspection equipment thereof

Growing community of inventors

Taoyuan, Taiwan

Wei-Chih Chen