Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Applied Materials, Inc.

Tuson (jiaxing) Corporation

Wei Chih Chen

Chin-Ming Fu

Chung-Hui Chen

Tsung-Hsin Yu

Wan-Te Chen

Shu-Chun Yang

Chi-Chang Lu

Mei Yin Chang

Yen-Yu Chen

Ruey-Bin Sheen

Cheng-Hsiang Hsieh

Mu-Shan Lin

Marvin De-Dui Liao

Yu-Nan Shih

Tzu Ching Chang

Chyi Chern

Jennifer Meng Tseng

Wen-Shen Ko

Chih-Han Ko

Wang-Hsiang Ko

Yen Le Lee

Richard Fay

Paul Peng

Gino Tsai

Roger H Tu

J Fan Chang

Tai Hsiang Liao

Kai-Ping Chan

A method of manufacturing a semiconductor device based on a dual-architecture-compatible design includes: forming transistor components of in a transistor (TR) layer; and performing one of fabricating additional components according to (A) a buried power rail (BPR) type of architecture or (B) a non-buried power rail (non-BPR) type of architecture. The step (A) includes, in corresponding sub-TR layers, forming various non-dummy sub-TR structures, and, in corresponding supra-TR layers, forming various dummy supra-TR structures which are corresponding first artifacts. The step (B) includes, in corresponding supra-TR layers, forming various non-dummy supra-TR structures and forming various dummy supra-TR structures which are corresponding second artifacts, the first and second artifacts resulting from the dual-architecture-compatible design being suitable to adaptation into the BPR type of architecture.

Method of fabricating semiconductor devices having different architectures and semiconductor devices fabricated thereby

Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.

Systems and methods for multi-phase clock generation

An overhead transport vehicle is described for association with an Automated Material Handling System (AMHS). The overhead transport vehicle provides features to the AMHS by which the AMHS is able to reduce a number of manual urgent lot rescues by the fab operator when a logistic algorithm controlling traffic in the AMHS is unable to transport the front opening unified pods (FOUP) from one tool to the subsequent tool in the sequence of the process steps within the q-time due to unexpected problems. An indicator on the overhead transport vehicle which helps the fab operator with spotting a lot in trouble is described. A backup power source on the overhead transport vehicle used in case of a main power failure is also described.

Automated material handling systems

An integrated circuit (IC) structure includes a semiconductor substrate, a bottom electrode routing, a capacitor structure, a top electrode routing. The bottom electrode routing is over the semiconductor substrate. The capacitor structure is over the bottom electrode routing. The capacitor structure includes a bottom metal layer, a middle metal layer above the bottom metal layer, and a top metal layer above the middle metal layer. When viewed in a plan view, the top metal layer has opposite straight edges extending along a first direction and opposite square wave-shaped edges connecting the opposite straight edges, the square wave-shaped edges each comprise alternating first and second segments extending along a second direction perpendicular to the first direction, and third segments each connecting adjacent two of the first and second segments, wherein the third segments extend along the first direction.

Capacitor and method for forming the same

A reusable adhesive pad with embedded magnets consists of a layer of fibrous cloth with elasticity, a layer of silicone gel padding, and permanent magnets. The fibrous cloth with elasticity is made from fiber materials with a stretchable characteristic. The silicone gel padding is spread out fully and glued on one surface of the fibrous cloth with elasticity. In addition, the silicone gel padding is provided with holes that the permanent magnets with cylindrical or conical outers can be filled in and glued to the adhesive surface of the fibrous cloth with elasticity. Since the other sides of the permanent magnets protrude outwards the surface of the silicone gel padding, applying the invention to the human skin can perform the acupuncture and moxibustion treatment and the magneto-therapy to lessen painful discomfort.

Reusable adhesive pad with embedded magnets

A amplifier circuit in some embodiment includes a differential amplifier have a pair of current sources. Each of the current sources includes two or more current-generating transistors and respective switching transistors, which can be turned on and off by a gain input code to tune the gain of the amplifier. A common-mode controller includes a similar pair of current sources as the differential amplifier. The common mode controller receives a common-mode signal of the input signal and a common-mode gain input code, and maintains the common-mode gain of the amplifier circuit when the differential gain changes. The amplifier circuit is switchable between a buffer mode and an equalizer mode.

Tunable gain amplifier

A calibration circuit for calibrating a device to be calibrated includes a variable current generator, a circuit component, and a control unit. The variable current generator generates a variable current responsive to variations of a supply voltage relative to a predetermined voltage level. The circuit component is a copy of at least one portion of the device to be calibrated and is coupled between the variable current generator and the supply voltage. The control unit is coupled to the variable current generator and the circuit component, and generates, based on a voltage dependent on the variable current and the circuit component, at least one calibration signal for adjusting an adjustable electrical parameter of the circuit component and the device to be calibrated.

Calibration circuit, integrated circuit having calibration circuit, and calibration method

The present invention relates to a trailer with a trailer brake control device therein. The trailer brake control device of the present invention comprises: a sway detecting sensor arranged in the trailer for detecting the sway of the trailer; a signal sensor for detecting a brake signal generated by a brake switch of a vehicle which tows the trailer; and a processor, electrically connected to the sway detecting sensor, the signal sensor and the brake, for controlling the brake based on an output of the sway detecting sensor and/or an output of the signal sensor. According to the present invention, the trailer brake control device can independently control the brakes and/or diagnose the malfunction of a brake controller arranged in the vehicle.

Trailer with a trailer brake control device therein

A system and method is disclosed for adjusting for timing variations between a data signal and an associated data read signal being transmitted from a first chip and received on a second chip.

System and method for chip system timing compensation

A high-swing voltage mode driver is provided that is operably coupled to a Serializer/Deserializer (SerDes) chip. The high-swing voltage mode driver can operate at a speed of 16 gigabits per second. The high-swing voltage mode driver comprises a thirteenth transistor that is configured to stabilize a voltage at a fifth node, where an output signal that is a negative differential signal exists. The high-swing voltage mode driver comprises a sixteenth transistor that is configured to stabilize a voltage at a sixth node, where an output signal that is a positive differential signal exists.

High-swing voltage mode driver

Some embodiments relate to a level detector, comprising a current mirror including first and second current legs to carry first and second signals, respectively. The first current leg includes a first variable resistor and the second current leg includes a second variable resistor. During a calibration mode, a switching element provides a predetermined reference voltage across first and second control terminals of the first and second variable resistors, respectively. During a non-calibration mode, the switching element decouples the predetermined reference voltage from the first and second control terminals, and provides a signal across the first and second control terminals. Other embodiments are also disclosed.

Voltage threshold calibration techniques for level detectors

Among other things, one or more systems and techniques for porting a circuit design from a first process design type to a second process design type are provided. A circuit design comprises one or more components, such as transistors, that are arranged and sized according to a first process design type, such as a 90 nm processing environment. The circuit design is partitioned into one or more topology categories such as a current mirror topology category or a differential pair topology category. Ordered sets of parameters are determined for respective topology categories. The components within the circuit design are resized based upon the one or more topology categories to generate a ported circuit design specified for the second process design type, such as a 50 nm processing environment.

Circuit design porting between process design types

A calibration circuit for calibrating a device to be calibrated includes a variable current generator, a device under test and a control unit. The variable current generator is coupled to a first node of a reference voltage and configured to generate a variable current responsive to variations of the reference voltage. The device under test is a copy of at least one portion of the device to be calibrated, and coupled to the variable current generator to derive, at a second node, a voltage dependent on the variable current. The control unit is coupled to the second node to receive the derived voltage and configured to compare the derived voltage with the reference voltage and to generate, based on a comparison result, at least one calibration signal for adjusting an adjustable electrical parameter of the device under test and the device to be calibrated.

Growing community of inventors

Hsinchu, Taiwan

Wei Chih Chen