Taiwan Semiconductor Manufacturing Comp. Ltd.

Global Unichip Corporation

Wei-Chieh Liao

Igor Elkanovich

Hung-Yi Chang

Li-Ken Yeh

Yu-Cheng Sun

Ming-Hsuan Wang

Hao-Yu Tung

Chung-Ling Liou

A routing structure between dies is provided, including a trace layer, disposed on a substrate, wherein a plurality of routing paths is embedded in the trace layer. In addition, a first die and a second die are disposed on the trace layer and connected by the routing paths. A spacing gap between the first die and the second die is along a first direction and interfacing edges of the first die and the second die are extending along a second direction perpendicular to the first direction. Each of the routing paths includes a first straight portion in parallel to connect to the interfacing edges. The first straight portion has a slant angle with respect to the first direction other than 0&#xb0; and 90&#xb0;.

Routing structure between dies and method for arranging routing between dies

A communication interface structure for connection between dies is provided, including a memory die, processing dies and interconnection routings. The memory die includes a first interface edge, wherein the first interface edge is split into a plurality of interface groups. Each of the processing dies includes a second interface edge. Interconnection routings respectively connect the second interface edges of the processing dies to the interface groups of the memory die.

Communication interface structure between processing die and memory die

Growing community of inventors

Hsinchu, Taiwan

Wei-Chieh Liao