Ememory Technology Inc.

Wei-Chiang Ong

Chih-Yang Huang

Wei-Ming Ku

Hsueh-Wei Chen

Yu Yuan Wu

Tsung-Ta Hsieh

Cheng-Yu Chung

A level shifting circuit includes a first-type level shifter, a second-type level shifter and a controller. The controller is connected to the output terminal of the first-type level shifter and the output terminal of the second-type level shifter. The level shifting circuit can be operated in different modes. In a standby mode, the logic level state of an output signal from the level shifting circuit is determined according to the logic level state of a shifted signal from the first-type level shifter. In a non-standby mode, the logic level state of the output signal from the level shifting circuit is determined according to the logic level state of a shifted signal from the second-type level shifter.

Level shifting circuit

A memory cell is connected to a source line, a bit line, a word line, an assist gate line and an erase line. When a program action is performed, a weak programming procedure is first performed on the memory cell, and then a strong programming procedure is performed on the memory cell. When the weak programming procedure is performed, an on voltage is provided to the word line, a first program voltage is provided to the source line, a ground voltage is provided to the bit line, a first assist gate voltage is provided to the assist gate line, and a first erase line voltage is provided to the erase line. When the strong programming procedure is performed, a lower program voltage and a higher assist gate voltage are provided to the memory cell.

Memory cell and array structure of non-volatile memory and associated control method

A charge pump circuit includes a power switch, a first pull-low circuit, an output pull-low circuit, a first charge pump stage and an output charge pump stage. The power switch receives an enabling signal. The first pull-low circuit and the output pull-low circuit receive a pull-low signal. The first charge pump stage includes a first boost capacitor used to receive a first phase signal, a first transfer transistor, a first gate-control transistor and a first storage capacitor used to receive a second phase signal. The output charge pump stage includes an output boost capacitor used to receive a third phase signal, an output transfer transistor and an output gate-control transistor. The charge pump circuit generates voltages in an erasing operation, a program operation and a read operation according to the enabling signal, the pull-low signal, the first phase signal, the second phase signal and the third phase signal.

Charge pump circuit capable of generating voltages in erasing operation, program operation and read operation

A voltage driver includes a voltage divider, a first transistor and a second transistor. The voltage divider is connected with a first voltage source and a second voltage source, and generates a first bias voltage. A drain terminal of the first transistor is connected with a third voltage source. A gate terminal of the first transistor is connected with the voltage divider to receive the first bias voltage. A drain terminal of the second transistor is connected with a source terminal of the first transistor. A gate terminal of the second transistor receives a second bias voltage. A source terminal of the second transistor is connected with a fourth voltage source. The first transistor and the second transistor are of the same conductivity type and match each other. The source terminal of the first transistor generates an output voltage.

Voltage driver for memory

A voltage control device includes a first charge pump, a first power switch, a second charge pump, a second power switch, and a third power switch. The first charge pump generates a first application voltage according to the first system voltage. The first power switch has a first input terminal for receiving the first system voltage, a second input terminal for receiving the first application voltage, and an output terminal. The second charge pump generates a second application voltage according to a voltage received by the input terminal of the second charge pump. The second power switch has an input terminal for receiving the second application voltage, and an output terminal. The third power switch has a first input terminal coupled to the output terminal of the first charge pump, a second input terminal coupled to the output terminal of the second charge pump, and an output terminal.

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Hsinchu, Taiwan

Wei-Chiang Ong