Taiwan Semiconductor Manufacturing Comp. Ltd.

Wei-Chiang Hung

Chih-Han Lin

Che-Cheng Chang

Wei-Hao Huang

Song-Bor Lee

Kuo Hui Chang

Hsiang-Yu Tsai

Ping-Chung Liu

A semiconductor device includes a fin structure, a source/drain region, a first inter-layer dielectric (ILD) layer, a first contact plug, and a second contact plug. The fin structure extends above a substrate. The source/drain region is in the fin structure. The first ILD layer is over the source/drain region. The first contact plug extends through the first ILD layer to a silicide region of the source/drain region. The second contact plug is over the first contact plug. The first contact plug has a protruding portion extending above the first ILD layer and laterally surrounding a lower part of the second contact plug.

Semiconductor device and formation method thereof

Examples of an integrated circuit and a method for forming the integrated circuit are provided herein. In some examples, a method includes receiving a substrate that includes: a plurality of fins extending above a remainder of the substrate; a first region that includes a first fence region that contains a first subset of the plurality of fins; and a second region that includes a second fence region that contains a second subset of the plurality of fins. The first region has a first performance characteristic, and the second region has a second performance characteristic that is different from the first. Based on the first performance characteristic, the first subset of the plurality of fins is recessed to a first height, and based on the second performance characteristic, the second subset of the plurality of fins is recessed to a second height that is less than the first height.

Integrated circuit device fins

A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; and a stress memorization technology (SMT) sidewall spacer over a sidewall of the gate stack. The gate stack includes a gate dielectric layer over the semiconductor substrate and a gate electrode over the gate dielectric layer. The SMT sidewall spacer provides a stress for a channel region beneath the gate stack.

Semiconductor structure and manufacturing method thereof

An integrated circuit (IC) design method includes providing a design layout of the IC and placing a first cell and a second cell into the design layout. The second cell is a mirror of the first cell. The method further includes dividing the first cell into a first plurality of segments and dividing the second cell into a second plurality of segments. A third cell is formed by connecting a first portion of the first plurality of segments with a first portion of the second plurality of segments. A fourth cell is formed by connecting a second portion of the first plurality of segments with a second portion of the second plurality of segments. The first, second, third and fourth cells each have substantially the same function.

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Changhua County, Taiwan

Wei-Chiang Hung