United Microelectronics Corp.

National Cheng-Kung University

Wei-Chi Lee

Chang-Hung Chen

Yu-Lin Wang

Po-Yu Yang

Cheng-Hsiung Chen

Jun-Jie Wang

Han-Tsun Wang

Mu-Kai Tsai

Tzu-Feng Chang

Tsz-Hui Kuo

Mei-Ying Fan

Guan-Shyan Lin

Chun-Hsien Huang

Chung-Yuan Lee

Yu-Tse Kuo

Shu-Ru Wang

Chun-Yen Tseng

Ching-Cheng Lung

Shu-Wei Yeh

Shui-Jinn Wang

A layout pattern of static random access memory at least includes a substrate, a plurality of fin structures on the substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate, the plurality of transistors include, a first pull-up transistor PU, a first pull-down transistor PD, a second pull-up transistor PU, a second pull-down transistor PD, a first pass gate transistor PG, a second pass gate transistor PG, a first read transistor RPD and a second read transistor RPG, and an additional fin structure, the additional fin structure is located between the fin structure of the first pass gate transistor PGand the fin structure of the second read transistor RPG.

Layout pattern of static random access memory and the manufacturing method thereof

A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure has a first line terminal. The second circuit structure has a second line terminal. The first line terminal and the second line terminal are formed in a first circuit layer but separated by a gap. A conductive structure is forming in a second circuit layer above or below the first circuit layer, to electrically connect the first line terminal and the second line terminal.

Semiconductor device and semiconductor apparatus

An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. Agate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.

Method of adjusting signal to noise ratio of SRAM and invertor structure

The present invention provides a layout pattern of a static random access memory (SRAM). The layout pattern includes a first inverter and a second inverter constituting a latch circuit, wherein the latch circuit includes four transistors, a first access transistor (PG) and a second access transistor (PG) being electrically connected to the latch circuit, wherein the first access transistor is electrically connected to a first word line and a first bit line, and the second access transistor is electrically connected to a second word line and a second bit line, the first access transistor has a first gate length, the first access transistor has a second gate length, and the first gate length is different from the second gate length, and two read transistors series connected to each other, wherein one of the two read transistors is connected to the latch circuit.

Layout pattern for SRAM and manufacturing methods thereof

An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. A gate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.

A layout pattern of a static random access memory, including a first inverter and a second inverter constituting a latch circuit. A first inner access transistor, a second inner access transistor, a first outer access transistor and a second outer access transistor are electrically connected to the latch circuit, wherein the first outer access transistor has a first gate length, the first inner access transistor has a second gate length, and the first gate length is different from the second gate length.

A semiconductor structure includes a SRAM cell having transistors defined by fins and metal gate stack structures. A transistor and a corresponding pick up cell are disposed in an extension direction of the fins. The transistor and the corresponding pick up cell have metal gate stack structures of the same type.

Memory structure and a method for forming the same

A mask set includes a first mask and a second mask. The first mask includes geometric patterns. The second mask includes at least a strip-shaped pattern with a first edge and a second edge opposite to the first edge. The strip-shaped pattern has a centerline along a long axis of the strip-shaped pattern. The first edge includes inwardly displaced segments shifting towards the centerline and each of the inwardly displaced segments overlaps each of the geometric patterns.

Mask set and method for fabricating semiconductor device by using the same

A method for roughening an epitaxy structure layer, including: providing an epitaxy structure layer; and etching a surface of the epitaxy structure layer by an excimer laser having an energy density of 1000 mJ/cmor less to form a roughened surface. In addition, a method for manufacturing a light-emitting diode having a roughened surface is provided.

Growing community of inventors

Tainan, Taiwan

Wei-Chi Lee